[SI-LIST] Re: need advice on DDR3 simulation / termination
- From: Romi Mayder <romi.mayder@xxxxxxxxxx>
- To: "Hermann.Ruckerbauer@xxxxxxxxxxxxx" <Hermann.Ruckerbauer@xxxxxxxxxxxxx>, "brian.p.moran@xxxxxxxxx" <brian.p.moran@xxxxxxxxx>, "'Nitin_Bhagwath@xxxxxxxxxx'" <Nitin_Bhagwath@xxxxxxxxxx>, "joel@xxxxxxxxxx" <joel@xxxxxxxxxx>, SI-List <si-list@xxxxxxxxxxxxx>
- Date: Thu, 1 May 2014 16:19:34 +0000
There are likely two factors at play - (1) the long trace delay of the package
and (2) the high IO pad capacitance of the Arria II GX memory controller.
Looking at the keyword [C_comp] in the IBIS file for the Arria II GX SSTL15 IO
standard shows a value of 7pF. Replacing the single lumped RLC values in the
IBIS file under the keyword [package] with a multiple stage RLC circuit will
help a little bit. Also, replacing the package model with an S-parameter model
will help more. However, the 7pF die capacitance will still cause reflections
when probing at the package pin. As a point of reference, you can take a look
at the [C_comp] value for some typical DDR3 memory devices and you will likely
find the value to be less than ~1.5pF.
The easiest solution is to always probe at the die when running simulations
using devices with high IO pad capacitance.
Kind regards
Romi
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Hermann Ruckerbauer
Sent: Thursday, May 01, 2014 8:49 AM
To: brian.p.moran@xxxxxxxxx; 'Nitin_Bhagwath@xxxxxxxxxx'; joel@xxxxxxxxxx;
SI-List
Subject: [SI-LIST] Re: need advice on DDR3 simulation / termination
Yes, the controller package size is always an issue. Especially when only
Single RLC models are delivered. This is just good enough for small DRAM
packages, but not for big controller packages (at higher DDR3
speeds) . I tend to make a multi segment model out of the single RLC for such
packages .. But usually this is manual work.
Even the Spec for the DRAM defines the signal at the ball I always simulate die
to die (still taking a look to the signal at the ball).
For Reads often the Controller is anyhow not specified so accurate (die or
ball)?
@ Brian: Intel does a great job in providing very detailed package models of
the CPUs .. unfortunatelly too detailed ..
There are bumps, multiple routing segments, vias, balls ... and the user needs
to build his own package model. Unfortunatelly there are some unknowns like the
routing length for different pins. I'm not sure if you are working with the
people doing package modelling for real products, but if so please try to
convince people that a single s-Parameter set (e. g. 11 lines for one byt on
DQ-Bus) is much more usefull for normal users ...
Regards
Hermann
Am 01.05.2014 07:52, schrieb Moran, Brian P:
> I absolutely agree. This is always a dilemma, because the specs of
> the controller tend to be defined at the pkg ball. However, you can
> not get an accurate waveform at the pkg ball. You are too far away from the
> die pad and the termination, in many cases. I would definitely recommend
> taking your measurements at the die-pad.
>
> Brian Moran
> Client Platforms
> Intel Corporation
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Bhagwath, Nitin
> Sent: Wednesday, April 30, 2014 10:45 PM
> To: joel@xxxxxxxxxx; SI-List
> Subject: [SI-LIST] Re: need advice on DDR3 simulation / termination
>
> Hello Joel,
>
> If you're measuring at the pin of the controller, you'll likely see the
> reflections caused by the FPGA packaging and other internal routing
> parasitics. They're often not very short from the BGA field to the die. You
> might want to simulate at the die when doing reads.
>
> Regards,
> -Nitin
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Joel Brown
> Sent: Friday, April 25, 2014 12:07 PM
> To: SI-List
> Subject: [SI-LIST] need advice on DDR3 simulation / termination
>
> I am working on a DDR3 design.
> It uses an older FPGA (Altera Arria II GX) which does does not support ODT
> or OCT so all termination has to be external.
> The company who is providing the FPGA and IP has a reference design where the
> termination is 56 ohms to VTT at the midpoint of the data lines and DQS
> lines. I have been trying to simulate this and getting some strange results.
> With the DDR3 using Micron's IBIS model driving the line and Altera's
> SSTL15 as the receiver the waveform is severely distorted. If I replace
> Altera's SSTL15 input with just a 10K resistor it looks much better. I don't
> know why the Altera's model for the receiver would cause the distortion since
> it should be high impedance with some small parasitics.
> Driving the other direction looks better but I get some high frequency
> ringing.
> I can send screen shots if it helps.
> Thanks
>
>
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