[SI-LIST] Re: need advice on DDR3 simulation / termination
- From: "Bhagwath, Nitin" <Nitin_Bhagwath@xxxxxxxxxx>
- To: "joel@xxxxxxxxxx" <joel@xxxxxxxxxx>, SI-List <si-list@xxxxxxxxxxxxx>
- Date: Thu, 1 May 2014 05:45:14 +0000
Hello Joel,
If you're measuring at the pin of the controller, you'll likely see the
reflections caused by the FPGA packaging and other internal routing parasitics.
They're often not very short from the BGA field to the die. You might want to
simulate at the die when doing reads.
Regards,
-Nitin
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Joel Brown
Sent: Friday, April 25, 2014 12:07 PM
To: SI-List
Subject: [SI-LIST] need advice on DDR3 simulation / termination
I am working on a DDR3 design.
It uses an older FPGA (Altera Arria II GX) which does does not support ODT or
OCT so all termination has to be external.
The company who is providing the FPGA and IP has a reference design where the
termination is 56 ohms to VTT at the midpoint of the data lines and DQS lines.
I have been trying to simulate this and getting some strange results.
With the DDR3 using Micron's IBIS model driving the line and Altera's
SSTL15 as the receiver the waveform is severely distorted. If I replace
Altera's SSTL15 input with just a 10K resistor it looks much better. I don't
know why the Altera's model for the receiver would cause the distortion since
it should be high impedance with some small parasitics.
Driving the other direction looks better but I get some high frequency ringing.
I can send screen shots if it helps.
Thanks
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