[SI-LIST] Re: need advice on DDR3 simulation / termination
- From: Hermann Ruckerbauer <Hermann.Ruckerbauer@xxxxxxxxxxxxx>
- To: Joel Brown <joel@xxxxxxxxxx>, Cuong Nguyen <cuong@xxxxxxxxxxxxx>
- Date: Fri, 02 May 2014 07:20:33 +0200
Hello Joel,
I have even seen package models with global values where the Vendor put
the input capacitance of the Power pins in max value of the package model.
But even if the max values are coming e. g. from a low speeed pin it
does not make sens to use such a max value.
So as long you do not really have the capacitance of the pins you want
to use it can be very misleading to use the max. value as you have seen.
Maybe you can get more information from Altera on this one ?
Hermann
Latest Download:
=================
Presentation to our paper on the Embedded World Conference 2014:
"Jitter in PCIe application on embedded boards with PLL Zero delay Clock buffer"
http://www.eyeknowhow.de/en/downloads/
EKH - EyeKnowHow
Hermann Ruckerbauer
www.EyeKnowHow.de
Hermann.Ruckerbauer@xxxxxxxxxxxxx
Itzlinger Strasse 21a
94469 Deggendorf
Tel.: +49 (0)991 / 29 69 29 05
Mobile: +49 (0)176 / 787 787 77
Fax: +49 (0)3212 / 121 9008
schrieb Joel Brown:
> Having started this thread I am surprised how many responses there
> were and and all good relevant ones.
> I found that the RLC and C_Comp values were responsible for the
> significant signal distortion.
> Altera only gives a single global min, typ, max value for all pins.
> There is a large spread between min max, for example the inductance
> varies from 2.57nH to 10.53nH.
> Ideally an S-Parameter model of the package would be better.
> The waveform may be acceptable using the min value but not with the
> max value.
> There really isn't anything in the design I can do to improve upon
> this as far as I know.
> So simulation isn't really telling me the design is going to work, its
> just giving me an idea of what might happen.
> Building a board will be the only way to find out.
>
>
>
> On Thu, May 1, 2014 at 9:51 AM, Cuong Nguyen <cuong@xxxxxxxxxxxxx
> <mailto:cuong@xxxxxxxxxxxxx>> wrote:
>
> If your end product is the chip(s) then it is understandable to
> look at just
> the die timing
> (for reads) but don't forget that the chip pins have to drive other
> components on the board
> (for writes). That is the chip vendors also need to ensure that the
> packaging model is well
> Modeled (ie. Spice if necessary) to help customers designing with
> their
> chip(s).
>
> If your end product is a board then in addition to looking at
> timings at the
> die (to analyze
> best possible timings) you also need to look at the effects of
> package pins,
> traces, vias,
> PDN filtering, etc...
> If your signaling at the board level is not "clean" (ie. overshoots,
> undershoots, ringing, etc..)
> These effects can cause issues to adjacent devices at the board level
> including crosstalks, EMI,
> plane noise, etc...
>
> It is the final product functionality that counts for the end
> customer and
> not just "my timings
> at my die pins are clean..."
>
> Cuong
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> <mailto:si-list-bounce@xxxxxxxxxxxxx>
> [mailto:si-list-bounce@xxxxxxxxxxxxx
> <mailto:si-list-bounce@xxxxxxxxxxxxx>] On
> Behalf Of Romi Mayder
> Sent: Thursday, May 01, 2014 9:20 AM
> To: Hermann.Ruckerbauer@xxxxxxxxxxxxx; brian.p.moran@xxxxxxxxx
> <mailto:brian.p.moran@xxxxxxxxx>;
> 'Nitin_Bhagwath@xxxxxxxxxx <mailto:Nitin_Bhagwath@xxxxxxxxxx>';
> joel@xxxxxxxxxx <mailto:joel@xxxxxxxxxx>; SI-List
> Subject: [SI-LIST] Re: need advice on DDR3 simulation / termination
>
> There are likely two factors at play - (1) the long trace delay of the
> package and (2) the high IO pad capacitance of the Arria II GX memory
> controller. Looking at the keyword [C_comp] in the IBIS file for
> the Arria
> II GX SSTL15 IO standard shows a value of 7pF. Replacing the
> single lumped
> RLC values in the IBIS file under the keyword [package] with a
> multiple
> stage RLC circuit will help a little bit. Also, replacing the
> package model
> with an S-parameter model will help more. However, the 7pF die
> capacitance
> will still cause reflections when probing at the package pin. As
> a point of
> reference, you can take a look at the [C_comp] value for some
> typical DDR3
> memory devices and you will likely find the value to be less than
> ~1.5pF.
>
> The easiest solution is to always probe at the die when running
> simulations
> using devices with high IO pad capacitance.
>
> Kind regards
> Romi
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> <mailto:si-list-bounce@xxxxxxxxxxxxx>
> [mailto:si-list-bounce@xxxxxxxxxxxxx
> <mailto:si-list-bounce@xxxxxxxxxxxxx>] On
> Behalf Of Hermann Ruckerbauer
> Sent: Thursday, May 01, 2014 8:49 AM
> To: brian.p.moran@xxxxxxxxx <mailto:brian.p.moran@xxxxxxxxx>;
> 'Nitin_Bhagwath@xxxxxxxxxx <mailto:Nitin_Bhagwath@xxxxxxxxxx>';
> joel@xxxxxxxxxx <mailto:joel@xxxxxxxxxx>;
> SI-List
> Subject: [SI-LIST] Re: need advice on DDR3 simulation / termination
>
> Yes, the controller package size is always an issue. Especially
> when only
> Single RLC models are delivered. This is just good enough for
> small DRAM
> packages, but not for big controller packages (at higher DDR3
> speeds) . I tend to make a multi segment model out of the single
> RLC for
> such packages .. But usually this is manual work.
>
> Even the Spec for the DRAM defines the signal at the ball I always
> simulate
> die to die (still taking a look to the signal at the ball).
> For Reads often the Controller is anyhow not specified so accurate
> (die or
> ball)?
>
> @ Brian: Intel does a great job in providing very detailed package
> models of
> the CPUs .. unfortunatelly too detailed ..
> There are bumps, multiple routing segments, vias, balls ... and
> the user
> needs to build his own package model. Unfortunatelly there are
> some unknowns
> like the routing length for different pins. I'm not sure if you
> are working
> with the people doing package modelling for real products, but if
> so please
> try to convince people that a single s-Parameter set (e. g. 11
> lines for one
> byt on DQ-Bus) is much more usefull for normal users ...
>
> Regards
>
> Hermann
>
> Am 01.05.2014 07:52, schrieb Moran, Brian P:
> > I absolutely agree. This is always a dilemma, because the specs of
> > the controller tend to be defined at the pkg ball. However, you can
> > not get an accurate waveform at the pkg ball. You are too far
> away from
> the die pad and the termination, in many cases. I would definitely
> recommend taking your measurements at the die-pad.
> >
> > Brian Moran
> > Client Platforms
> > Intel Corporation
> >
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
> <mailto:si-list-bounce@xxxxxxxxxxxxx>
> > [mailto:si-list-bounce@xxxxxxxxxxxxx
> <mailto:si-list-bounce@xxxxxxxxxxxxx>] On Behalf Of Bhagwath, Nitin
> > Sent: Wednesday, April 30, 2014 10:45 PM
> > To: joel@xxxxxxxxxx <mailto:joel@xxxxxxxxxx>; SI-List
> > Subject: [SI-LIST] Re: need advice on DDR3 simulation / termination
> >
> > Hello Joel,
> >
> > If you're measuring at the pin of the controller, you'll likely
> see the
> reflections caused by the FPGA packaging and other internal routing
> parasitics. They're often not very short from the BGA field to
> the die.
> You might want to simulate at the die when doing reads.
> >
> > Regards,
> > -Nitin
> >
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
> <mailto:si-list-bounce@xxxxxxxxxxxxx>
> > [mailto:si-list-bounce@xxxxxxxxxxxxx
> <mailto:si-list-bounce@xxxxxxxxxxxxx>] On Behalf Of Joel Brown
> > Sent: Friday, April 25, 2014 12:07 PM
> > To: SI-List
> > Subject: [SI-LIST] need advice on DDR3 simulation / termination
> >
> > I am working on a DDR3 design.
> > It uses an older FPGA (Altera Arria II GX) which does does not
> support
> ODT or OCT so all termination has to be external.
> > The company who is providing the FPGA and IP has a reference
> design where
> the termination is 56 ohms to VTT at the midpoint of the data
> lines and DQS
> lines. I have been trying to simulate this and getting some
> strange results.
> > With the DDR3 using Micron's IBIS model driving the line and
> Altera's
> > SSTL15 as the receiver the waveform is severely distorted. If I
> replace
> Altera's SSTL15 input with just a 10K resistor it looks much
> better. I don't
> know why the Altera's model for the receiver would cause the
> distortion
> since it should be high impedance with some small parasitics.
> > Driving the other direction looks better but I get some high
> frequency
> ringing.
> > I can send screen shots if it helps.
> > Thanks
> >
> >
> > ------------------------------------------------------------------
> > To unsubscribe from si-list:
> > si-list-request@xxxxxxxxxxxxx
> <mailto:si-list-request@xxxxxxxxxxxxx> with 'unsubscribe' in the
> Subject field
> >
> > or to administer your membership from a web page, go to:
> > //www.freelists.org/webpage/si-list
> >
> > For help:
> > si-list-request@xxxxxxxxxxxxx
> <mailto:si-list-request@xxxxxxxxxxxxx> with 'help' in the Subject
> field
> >
> >
> > List forum is accessible at:
> > http://tech.groups.yahoo.com/group/si-list
> >
> > List archives are viewable at:
> > //www.freelists.org/archives/si-list
> >
> > Old (prior to June 6, 2001) list archives are viewable at:
> > http://www.qsl.net/wb6tpu
> >
> >
> > ------------------------------------------------------------------
> > To unsubscribe from si-list:
> > si-list-request@xxxxxxxxxxxxx
> <mailto:si-list-request@xxxxxxxxxxxxx> with 'unsubscribe' in the
> Subject field
> >
> > or to administer your membership from a web page, go to:
> > //www.freelists.org/webpage/si-list
> >
> > For help:
> > si-list-request@xxxxxxxxxxxxx
> <mailto:si-list-request@xxxxxxxxxxxxx> with 'help' in the Subject
> field
> >
> >
> > List forum is accessible at:
> > http://tech.groups.yahoo.com/group/si-list
> >
> > List archives are viewable at:
> > //www.freelists.org/archives/si-list
> >
> > Old (prior to June 6, 2001) list archives are viewable at:
> > http://www.qsl.net/wb6tpu
> >
> >
> > ------------------------------------------------------------------
> > To unsubscribe from si-list:
> > si-list-request@xxxxxxxxxxxxx
> <mailto:si-list-request@xxxxxxxxxxxxx> with 'unsubscribe' in the
> Subject field
> >
> > or to administer your membership from a web page, go to:
> > //www.freelists.org/webpage/si-list
> >
> > For help:
> > si-list-request@xxxxxxxxxxxxx
> <mailto:si-list-request@xxxxxxxxxxxxx> with 'help' in the Subject
> field
> >
> >
> > List forum is accessible at:
> > http://tech.groups.yahoo.com/group/si-list
> >
> > List archives are viewable at:
> > //www.freelists.org/archives/si-list
> >
> > Old (prior to June 6, 2001) list archives are viewable at:
> > http://www.qsl.net/wb6tpu
> >
> >
>
>
> --
> Latest Download:
> =================
> Presentation to our paper on the Embedded World Conference 2014:
> "Jitter in PCIe application on embedded boards with PLL Zero delay
> Clock
> buffer"
> http://www.eyeknowhow.de/en/downloads/
>
> EKH - EyeKnowHow
> Hermann Ruckerbauer
> www.EyeKnowHow.de <http://www.EyeKnowHow.de>
> Hermann.Ruckerbauer@xxxxxxxxxxxxx
> Itzlinger Strasse 21a
> 94469 Deggendorf
> Tel.: +49 (0)991 / 29 69 29 05
> <tel:%2B49%20%280%29991%20%2F%2029%2069%2029%2005>
> Mobile: +49 (0)176 / 787 787 77
> <tel:%2B49%20%280%29176%20%20%2F%20787%20787%2077>
> Fax: +49 (0)3212 / 121 9008
> <tel:%2B49%20%280%293212%20%2F%20121%209008>
>
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request@xxxxxxxxxxxxx
> <mailto:si-list-request@xxxxxxxxxxxxx> with 'unsubscribe' in the
> Subject field
>
> or to administer your membership from a web page, go to:
> //www.freelists.org/webpage/si-list
>
> For help:
> si-list-request@xxxxxxxxxxxxx
> <mailto:si-list-request@xxxxxxxxxxxxx> with 'help' in the Subject
> field
>
>
> List forum is accessible at:
> http://tech.groups.yahoo.com/group/si-list
>
> List archives are viewable at:
> //www.freelists.org/archives/si-list
>
> Old (prior to June 6, 2001) list archives are viewable at:
> http://www.qsl.net/wb6tpu
>
>
>
>
>
> This email and any attachments are intended for the sole use of
> the named
> recipient(s) and contain(s) confidential information that may be
> proprietary, privileged or copyrighted under applicable law. If
> you are not
> the intended recipient, do not read, copy, or forward this email
> message or
> any attachments. Delete this email message and any attachments
> immediately.
>
>
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request@xxxxxxxxxxxxx
> <mailto:si-list-request@xxxxxxxxxxxxx> with 'unsubscribe' in the
> Subject field
>
> or to administer your membership from a web page, go to:
> //www.freelists.org/webpage/si-list
>
> For help:
> si-list-request@xxxxxxxxxxxxx
> <mailto:si-list-request@xxxxxxxxxxxxx> with 'help' in the Subject
> field
>
>
> List forum is accessible at:
> http://tech.groups.yahoo.com/group/si-list
>
> List archives are viewable at:
> //www.freelists.org/archives/si-list
>
> Old (prior to June 6, 2001) list archives are viewable at:
> http://www.qsl.net/wb6tpu
>
>
>
>
>
>
> --
>
> */Joel Brown/*/*
> */
>
> Senior Electrical Design Engineer
>
> *Z Microsystems, Inc.*
>
> 9820 Summers Ridge Rd.
>
> San Diego, CA 92121
>
> Tel: 858-831-7011
>
> Fax: 858-831-7001
>
> joel@xxxxxxxxxx<mailto:joel@xxxxxxxxxx>
>
> http://www.zmicro.com<http://www.zmicro.com/>
>
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
