[SI-LIST] need advice on DDR3 simulation / termination
- From: Joel Brown <joel@xxxxxxxxxx>
- To: SI-List <si-list@xxxxxxxxxxxxx>
- Date: Fri, 25 Apr 2014 12:06:59 -0700
I am working on a DDR3 design.
It uses an older FPGA (Altera Arria II GX) which does does not support ODT
or OCT so all termination has to be external.
The company who is providing the FPGA and IP has a reference design where
the termination is 56 ohms to VTT at the midpoint of the data lines and DQS
lines. I have been trying to simulate this and getting some strange results.
With the DDR3 using Micron's IBIS model driving the line and Altera's
SSTL15 as the receiver the waveform is severely distorted. If I replace
Altera's SSTL15 input with just a 10K resistor it looks much better. I
don't know why the Altera's model for the receiver would cause the
distortion since it should be high impedance with some small parasitics.
Driving the other direction looks better but I get some high frequency
ringing.
I can send screen shots if it helps.
Thanks
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