[SI-LIST] Re: need advice on DDR3 simulation / termination

  • From: Hermann Ruckerbauer <Hermann.Ruckerbauer@xxxxxxxxxxxxx>
  • To: hanymhfahmy@xxxxxxxxxxxxxxxxxxx, brian.p.moran@xxxxxxxxx, Nitin_Bhagwath@xxxxxxxxxx, joel@xxxxxxxxxx, 'SI-List' <si-list@xxxxxxxxxxxxx>
  • Date: Fri, 02 May 2014 07:15:20 +0200

Hello Hany,
I agree there is always a tradeoff between accuracy and usability.
While some controller vendors does make things simple to use by
providing just a simple RLC model Intel makes things very accurate but
not really user friendly.

Yes, it's the controller vendors responsibility to find out worst case
corners for the package .. but for the user it is enough to provide this
as result, and not leave it to the user to find out that again.
I know that this is not completely true, as the users system worst case
corner might be different to intels system, but Intel give quite
detailed DesignGuides and if these are followed the worst case corner
should not be that different. So S-Parameter models (if really required
three corners of the package) should be good enough for 99% of the
implementers out there.

You are looking at the problem from a Pre-Development point of view. In
this case the worst case corner need to be figured out. For people who
are just implementing a current available or new CPU it is important to
get the job done FAST. This people don't have the time and quite often
they do not even simulate .. they just try to follow the design guide
(as good as possible).

So we need this tradeoff between accuracy and usability, and just with
S-parameters we would be good enough for most usage cases.

Hermann

Latest Download:
=================
Presentation to our paper on the Embedded World Conference 2014:
"Jitter in PCIe application on embedded boards with PLL Zero delay Clock buffer"
http://www.eyeknowhow.de/en/downloads/

EKH - EyeKnowHow
Hermann Ruckerbauer
www.EyeKnowHow.de
Hermann.Ruckerbauer@xxxxxxxxxxxxx
Itzlinger Strasse 21a
94469 Deggendorf
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schrieb Hany Fahmy:
>
> @ Hermann: actually Intel provides also a spreadsheet showing in
> detail the length of each pin that can be dialed-in the models.
>
>  
>
> The models r needed this way (w details of bumps, break-out from
> die-bump area, main-TL, back routing, ....etc.) since we can simulate
> different corners and also some bytes r routed MS while others routed
> SL, so a single S-model is not enough and is not accurate to cover all
> HVM corners and all different byte lane routing.
>
>  
>
> As I mentioned, on CPUs and GPUs, not all byte lanes r routed on a
> single layer, some of them routed as MS and others SL n interfaces
> such as DDR4-3200 need such accuracy of different HVM and different
> routing of the lanes. It is our responsibility to find out the
> worst-case corner and worst-case byte lanes to provide accurate
> simulations that correlate to lab data.
>
>  
>
> Hany Fahmy
>
> CEO & Chief Consultant Officer
>
> Intelligent Solutions BVBA
>
>                  
>
> hanymhfahmy@xxxxxxxxxxxxxxxxxxx
>
> http://www.intelligentsolutionsbvba.com/
>
> http://www.linkedin.com/pub/hany-fahmy/66/852/b11
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> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Hermann Ruckerbauer
> Sent: Thursday, May 1, 2014 5:49 PM
> To: brian.p.moran@xxxxxxxxx; 'Nitin_Bhagwath@xxxxxxxxxx';
> joel@xxxxxxxxxx; SI-List
> Subject: [SI-LIST] Re: need advice on DDR3 simulation / termination
>
>  
>
> Yes, the controller package size is always an issue. Especially when
> only Single RLC models are delivered. This is just good enough for
> small DRAM packages, but not for big controller packages  (at higher DDR3
>
> speeds) . I tend to make a multi segment model out of the single RLC
> for such packages .. But usually this is manual work.
>
>  
>
> Even the Spec for the DRAM defines the signal at the ball I always
> simulate die to die (still taking a look to the signal at the ball).
>
> For Reads often the Controller is anyhow not specified so accurate
> (die or ball)?
>
>  
>
> @ Brian: Intel does a great job in providing very detailed package
> models of the CPUs .. unfortunatelly too detailed ..
>
> There are bumps, multiple routing segments, vias, balls ... and the
> user needs to build his own package model. Unfortunatelly there are
> some unknowns like the routing length for different pins. I'm not sure
> if you are working with the people doing package modelling for real
> products, but if so please try to convince people that a single
> s-Parameter set (e. g. 11 lines for one byt on DQ-Bus) is much more
> usefull for normal users ...
>
>  
>
> Regards
>
>  
>
> Hermann
>
>  
>
> Am 01.05.2014 07:52, schrieb Moran, Brian P:
>
> > I absolutely agree.  This is always a dilemma, because the specs of
>
> > the controller tend to be defined at the pkg ball.  However, you can
>
> > not get an accurate waveform at the pkg ball.  You are too far away
> from the die pad and the termination, in many cases.  I would
> definitely recommend taking your measurements at the die-pad.
>
> > 
>
> > Brian Moran
>
> > Client Platforms
>
> > Intel Corporation
>
> > 
>
> > -----Original Message-----
>
> > From: si-list-bounce@xxxxxxxxxxxxx
> <mailto:si-list-bounce@xxxxxxxxxxxxx>
>
> > [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Bhagwath, Nitin
>
> > Sent: Wednesday, April 30, 2014 10:45 PM
>
> > To: joel@xxxxxxxxxx <mailto:joel@xxxxxxxxxx>; SI-List
>
> > Subject: [SI-LIST] Re: need advice on DDR3 simulation / termination
>
> > 
>
> > Hello Joel,
>
> > 
>
> > If you're measuring at the pin of the controller, you'll likely see
> the reflections caused by the FPGA packaging and other internal
> routing parasitics.  They're often not very short from the BGA field
> to the die.  You might want to simulate at the die when doing reads.
>
> > 
>
> > Regards,
>
> > -Nitin
>
> > 
>
> > -----Original Message-----
>
> > From: si-list-bounce@xxxxxxxxxxxxx
> <mailto:si-list-bounce@xxxxxxxxxxxxx>
>
> > [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Joel Brown
>
> > Sent: Friday, April 25, 2014 12:07 PM
>
> > To: SI-List
>
> > Subject: [SI-LIST] need advice on DDR3 simulation / termination
>
> > 
>
> > I am working on a DDR3 design.
>
> >  It uses an older FPGA (Altera Arria II GX) which does does not
> support ODT or OCT so all termination has to be external.
>
> > The company who is providing the FPGA and IP has a reference design
> where the termination is 56 ohms to VTT at the midpoint of the data
> lines and DQS lines. I have been trying to simulate this and getting
> some strange results.
>
> > With the DDR3 using Micron's IBIS model driving the line and Altera's
>
> > SSTL15 as the receiver the waveform is severely distorted. If I
> replace Altera's SSTL15 input with just a 10K resistor it looks much
> better. I don't know why the Altera's model for the receiver would
> cause the distortion since it should be high impedance with some small
> parasitics.
>
> > Driving the other direction looks better but I get some high
> frequency ringing.
>
> > I can send screen shots if it helps.
>
> > Thanks
>
> > 
>
> > 
>
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>  
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>  
>
> --
>
> Latest Download:
>
> =================
>
> Presentation to our paper on the Embedded World Conference 2014:
>
> "Jitter in PCIe application on embedded boards with PLL Zero delay
> Clock buffer"
>
> http://www.eyeknowhow.de/en/downloads/
>
>  
>
> EKH - EyeKnowHow
>
> Hermann Ruckerbauer
>
> www.EyeKnowHow.de <http://www.EyeKnowHow.de>
>
> Hermann.Ruckerbauer@xxxxxxxxxxxxx
> <mailto:Hermann.Ruckerbauer@xxxxxxxxxxxxx>
>
> Itzlinger Strasse 21a
>
> 94469 Deggendorf
>
> Tel.:       +49 (0)991 / 29 69 29 05
>
> Mobile: +49 (0)176  / 787 787 77
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