[SI-LIST] Re: Traces don't cause EMI - really?
- From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
- To: "Ken Hayden" <khayden@xxxxxxxxxxxxxxxxxx>, MikonCons@xxxxxxx
- Date: Sun, 1 Feb 2004 09:43:43 -0800
Ken,
If you log onto the Procket web site, www.procket.com, you will see a
terabit router as one of their products. Every PCB in that box has signals
as fast as 2.4 GB/S. In every case some or many of these signals are
routed on the outer layers, or more precisely layer 2 and n-1, with the two
outer layers being "cap" or no signal layers. This box passed CISPRA on
its first test and CISPRB on its second test after some gaskets were
improved. In no case did any PCB interfere with any other PCB.
I've designed high performance products using this technique for more than
20 years with good success in every product. I'm not sure where the notion
that traces on outer layers causes problems comes from, but is had never
been a problem with any product I have designed.
Don't worry about it. Just make sure the ground planes are not split and
that you do a good job designing with your power decoupling.
Lee
> [Original Message]
> From: Ken Hayden <khayden@xxxxxxxxxxxxxxxxxx>
> To: <MikonCons@xxxxxxx>
> Cc: <si-list@xxxxxxxxxxxxx>
> Date: 1/30/2004 5:00:46 AM
> Subject: [SI-LIST] Re: Traces don't cause EMI - really?
>
> I read this thread last fall with great interest, and I think I learned a
lot. But I
> have an immediate application about which I'm still confused, and could
use some help.
>
> This application is for a PCB that will be assembled into a shielded card
cage
> assembly. This particular PCB will not have any cables leaving the
shielded enclosure,
> but any number of other PCBs in this 36-card assembly could have cables
of various
> geometries and filtering characteristics. (This is a telecom/datacom
application, and
> the PCBs are line cards with numerous flavors of DSL, Ethernet, POTS, and
digital
> telecom interfaces.)
>
> We have traditionally laid out PCBs for this application with outside
planes, and
> absolutely everthing with any high-frequency content was run on inside
signal layers.
> Using this kind of stackup, and taking many of the usual precautions, we
have had good
> success in building cards that pass FCC class A, and usually class B.
>
> In the current (very quick-turn) project, we will be using an embedded
microprocessor we
> haven't used before. In the interest of building fully functional boards
with good
> signal and power integrity as quickly as possible, we are considering
directly lifting
> the processor, DDR SDRAM, gigabit GMII, PCI, and HyperTransport artwork
section from the
> microprocessor vendor's evaluation kit artwork, and incorporating the
artwork into the
> rest of our design.
>
> It turns out that this evaluation kit is in PCI plug-in board format
(clearly intended
> to run in a desktop PC), and has the following stackup:
>
> TOP
> GND
> SIG1
> GND
> PWR
> PWR
> GND
> SIG2
> GND
> BOT
>
> This is of course a wonderful stackup for power distribution, but it
requires running
> close to half of the signals on the outside layers, since there are only
two internal
> signal layers. The evaluation kit runs many of the DDR SDRAM, PCI, and
GMII traces on
> the top and bottom layers. Only clocks and HyperTransport traces seem to
be strictly
> limited to SIG1 and SIG2.
>
> My question is this: Is this kind of layout likely to radiate
significantly into other
> boards in the enclosure (relative to a board with more layers, having
added planes
> outside all signal layers), thereby risking excessive CM currents from
the cables
> leading from these other boards? As I have mentioned, we have always
believed that it
> would, and have avoided such a stackup. But I wonder if we've been going
overboard and
> wasting money on extra layers.
>
> Ken Hayden
> Consulting Engineer
> Integral Access
>
>
>
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