[SI-LIST] Re: Traces don't cause EMI - really?
- From: "Grasso, Charles" <Charles.Grasso@xxxxxxxxxxxx>
- To: 'Ken Hayden' <khayden@xxxxxxxxxxxxxxxxxx>
- Date: Mon, 2 Feb 2004 09:47:11 -0700
Ken,
My responses are buried in with your questions:
[Ken] If I'm not mistaken, the presentation makes the point that EMI
generated by the plane voltage drop (caused by signal return current) will
generally dominate over EMI from the current loop formed by the signal trace
and its return current.
[Chas] That correct. The seminal work behind the papers referenced was
that there really is an inductance that is associated by the ground plane
and that it is affected by the trace height above the plane and the plane
dimensions.
[Ken] As I understand it, the effect of that plane drop would be to cause
the whole plane to take on an RF voltage, possibly with standing waves
(resonances) as discussed elsewhere in this forum.
[Chas] I agree.
[Ken]1. Wouldn't the net effect of adding another ground plane outside such
a trace simply be to reduce the ground drop by less than half, as a result
of adding a second parallel return plane (that's coupled to the first plane
fairly closely)?
[Chas] A measure of the ground drop is the emissions profile. This
configuration was physically modeled and measured (by R. German & R. Dockey)
and they found that
a) if the top plane is coupled (but not attached to) the bottom plane
emissions were increased at the resonant frequencies by as much as 40dB
b) emissions were reduced more than 30dB (way more than half!)at all
frequencies until the slots between the plane terminations became resonant.
[Ken]2. What about skin effect? I understand that at frequencies of
interest (hundreds of MHz and up), the skin depth is only a fraction of the
thickness of the copper plane. This implies that the plane voltage drop
induced on the inside of an outer plane could not "penetrate" to the
outside to radiate.
[Chas] Correct. A simple experiment with a loop probe will confirm that.
{Ken] 2(b)By extension, if an overall outer ground plane was used, there
would be no plane voltage drop detectable on the outside of the plane. (I
know this is nonsense, but I don't know where my logic is failing.)
[Chas] Generally what you describe (a "box" made up of two planes and vias)
has been tested and measured as a very effective method of minimizing
emissions for the reasons you describe. Not many of us can afford to
implement this though!
For an through analysis I would refer you to "New Techniques for Reducing
Printed Circuit Board Common-Mode Radiation" by Dockey and German.
Best Regards
Charles Grasso
Senior Compliance Engineer
Echostar Communications Corp.
Tel: 303-706-5467
Fax: 303-799-6222
Cell: 303-204-2974
Email: charles.grasso@xxxxxxxxxxxx;
Email Alternate: chasgrasso@xxxxxxxx
-----Original Message-----
From: Ken Hayden [mailto:khayden@xxxxxxxxxxxxxxxxxx]
Sent: Friday, January 30, 2004 7:56 AM
To: Grasso, Charles
Cc: 'si-list@xxxxxxxxxxxxx'
Subject: Re: [SI-LIST] Re: Traces don't cause EMI - really?
Thanks for reminding me of Dr. Bogatin's presentation, Charles. I read it
when
the si-list first pointed it out, and it's a refreshingly clear treatment of
the
subject. If I'm not mistaken, the presentation makes the point that EMI
generated by the plane voltage drop (caused by signal return current) will
generally dominate over EMI from the current loop formed by the signal trace
and
its return current. As I understand it, the effect of that plane drop would
be
to cause the whole plane to take on an RF voltage, possibly with standing
waves
(resonances) as discussed elsewhere in this forum. If that's the case, I
have
two questions:
1. Wouldn't the net effect of adding another ground plane outside such a
trace
simply be to reduce the ground drop by less than half, as a result of adding
a
second parallel return plane (that's coupled to the first plane fairly
closely)?
2. What about skin effect? I understand that at frequencies of interest
(hundreds of MHz and up), the skin depth is only a fraction of the thickness
of
the copper plane. This implies that the plane voltage drop induced on the
inside of an outer plane could not "penetrate" to the outside to radiate.
By
extension, if an overall outer ground plane was used, there would be no
plane
voltage drop detectable on the outside of the plane. (I know this is
nonsense,
but I don't know where my logic is failing.)
-Ken
"Grasso, Charles" wrote:
> Ken you may be interested in looking at a presentation made by
> Dr Bogatin that addressed this very subjecy.
> you can find it at http://www.ieee.org/rmcemc go to the archives
> and look for the 2003 December meeting.
>
> Cheers
>
> Best Regards
> Charles Grasso
> Senior Compliance Engineer
> Echostar Communications Corp.
> Tel: 303-706-5467
> Fax: 303-799-6222
> Cell: 303-204-2974
> Email: charles.grasso@xxxxxxxxxxxx;
> Email Alternate: chasgrasso@xxxxxxxx
>
>
> -----Original Message-----
> From: Ken Hayden [mailto:khayden@xxxxxxxxxxxxxxxxxx]
> Sent: Friday, January 30, 2004 6:00 AM
> To: MikonCons@xxxxxxx
> Cc: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Traces don't cause EMI - really?
>
> I read this thread last fall with great interest, and I think I learned a
> lot. But I
> have an immediate application about which I'm still confused, and could
use
> some help.
>
> This application is for a PCB that will be assembled into a shielded card
> cage
> assembly. This particular PCB will not have any cables leaving the
shielded
> enclosure,
> but any number of other PCBs in this 36-card assembly could have cables of
> various
> geometries and filtering characteristics. (This is a telecom/datacom
> application, and
> the PCBs are line cards with numerous flavors of DSL, Ethernet, POTS, and
> digital
> telecom interfaces.)
>
> We have traditionally laid out PCBs for this application with outside
> planes, and
> absolutely everthing with any high-frequency content was run on inside
> signal layers.
> Using this kind of stackup, and taking many of the usual precautions, we
> have had good
> success in building cards that pass FCC class A, and usually class B.
>
> In the current (very quick-turn) project, we will be using an embedded
> microprocessor we
> haven't used before. In the interest of building fully functional boards
> with good
> signal and power integrity as quickly as possible, we are considering
> directly lifting
> the processor, DDR SDRAM, gigabit GMII, PCI, and HyperTransport artwork
> section from the
> microprocessor vendor's evaluation kit artwork, and incorporating the
> artwork into the
> rest of our design.
>
> It turns out that this evaluation kit is in PCI plug-in board format
> (clearly intended
> to run in a desktop PC), and has the following stackup:
>
> TOP
> GND
> SIG1
> GND
> PWR
> PWR
> GND
> SIG2
> GND
> BOT
>
> This is of course a wonderful stackup for power distribution, but it
> requires running
> close to half of the signals on the outside layers, since there are only
two
> internal
> signal layers. The evaluation kit runs many of the DDR SDRAM, PCI, and
GMII
> traces on
> the top and bottom layers. Only clocks and HyperTransport traces seem to
be
> strictly
> limited to SIG1 and SIG2.
>
> My question is this: Is this kind of layout likely to radiate
significantly
> into other
> boards in the enclosure (relative to a board with more layers, having
added
> planes
> outside all signal layers), thereby risking excessive CM currents from the
> cables
> leading from these other boards? As I have mentioned, we have always
> believed that it
> would, and have avoided such a stackup. But I wonder if we've been going
> overboard and
> wasting money on extra layers.
>
> Ken Hayden
> Consulting Engineer
> Integral Access
>
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