[SI-LIST] Re: Traces don't cause EMI - really?
- From: "Vishram Pandit" <vishrampandit@xxxxxxxxxxx>
- To: khayden@xxxxxxxxxxxxxxxxxx, Charles.Grasso@xxxxxxxxxxxx
- Date: Fri, 30 Jan 2004 18:37:08 +0000
Ken,
Here is my 2c. on it:
2] Evenif the skin dept is smaller, the signals can travel on the plane and
can radiate from the edge of the board. It need not be necessarily from the
top surface. If you use ground guard band at the edge of the board or use
shorting vias at the edge of the board, you can reduce the radiation from
theedges. However, the noise signal will get reflected and may interfere
withthe wanted signals. Also, it may get into the PDS structure and get
coupled to different elements in the PDS (like vias) and get radiated from
there. Therefore, it is important to eliminate these signals at the source.
1] It will depend on where and how the ground plane is added. If you add a
ground plane so as to make power and ground coupling more tight (and reduce
the P/G impedance), then it will be helpful. If your existing ground plane
isnearer to the power plane than the new ground plane, then the same
phenominon of edge radiation exists.
Thanks and regards,
Vishram
>From: Ken Hayden >Reply-To: khayden@xxxxxxxxxxxxxxxxxx >To: "Grasso,
Charles" >CC: "'si-list@xxxxxxxxxxxxx'" >Subject: [SI-LIST] Re: Traces don't
cause EMI - really? >Date: Fri, 30 Jan 2004 09:56:24 -0500 >>Thanks for
reminding me of Dr. Bogatin's presentation, Charles. I read it when >the
si-list first pointed it out, and it's a refreshingly clear treatment of the
>subject. If I'm not mistaken, the presentation makes the point that EMI
>generated by the plane voltage drop (caused by signal return current) will
>generally dominate over EMI from the current loop formed by the signal
traceand >its return current. As I understand it, the effect of that plane
drop would be >to cause the whole plane to take on an RF voltage, possibly
with standing waves >(resonances) as discussed elsewhere in this forum. If
that's the case, I have >two questions: >1. Wouldn't the net effect of
addinganother ground plane outside such a trace >simply be to reduce the
ground drop by less than half, as a result of adding a >second parallel
return plane (that's coupled to the first plane fairly >closely)? >2. What
about skin effect? I understand that at frequencies of interest >(hundreds
of MHz and up), the skin depth is only a fraction of the thickness of >the
copper plane. This implies that the plane voltage drop induced on the
>inside of an outer plane could not "penetrate" to the outside to radiate.
By >extension, if an overall outer ground plane was used, there would be no
plane >voltage drop detectable on the outside of the plane. (I know this is
nonsense, >but I don't know where my logic is failing.) >-Ken >>"Grasso,
Charles" wrote: >>>Ken you may be interested in looking at a presentation
made by >>Dr Bogatin that addressed this very subjecy. >>you can find it at
http://www.ieee.org/rmcemc go to the archives >>and look for the 2003
December meeting. >>>>Cheers >>>>Best Regards >>Charles Grasso >>Senior
Compliance Engineer >>Echostar Communications Corp. >>Tel: 303-706-5467
>>Fax: 303-799-6222 >>Cell: 303-204-2974 >>Email:
charles.grasso@xxxxxxxxxxxx; >>Email Alternate: chasgrasso@xxxxxxxx
>>>>>>-----Original Message----- >>From: Ken Hayden
[mailto:khayden@xxxxxxxxxxxxxxxxxx] >>Sent: Friday, January 30, 2004 6:00 AM
>>To: MikonCons@xxxxxxx >>Cc: si-list@xxxxxxxxxxxxx >>Subject: [SI-LIST] Re:
Traces don't cause EMI - really? >>>>I read this thread last fall with great
interest, and I think I learned a >>lot. But I >>have an immediate
application about which I'm still confused, and could use >>some help.
>>>>This application is for a PCB that will be assembled into a shielded
card>>cage >>assembly. This particular PCB will not have any cables leaving
the shielded >>enclosure, >>but any number of other PCBs in this 36-card
assembly could have cables of >>various >>geometries and filtering
characteristics. (This is a telecom/datacom >>application, and >>the PCBs
are line cards with numerous flavors of DSL, Ethernet, POTS, and >>digital
>>telecom interfaces.) >>>>We have traditionally laid out PCBs for this
application with outside >>planes, and >>absolutely everthing with any
high-frequency content was run on inside >>signal layers. >>Using this kind
of stackup, and taking many of the usual precautions, we >>have had good
>>success in building cards that pass FCC class A, and usually class B.
>>>>In the current (very quick-turn) project, we will be using an embedded
>>microprocessor we >>haven't used before. In the interest of building
fullyfunctional boards >>with good >>signal and power integrity as quickly
aspossible, we are considering >>directly lifting >>the processor, DDR
SDRAM,gigabit GMII, PCI, and HyperTransport artwork >>section from the
>>microprocessor vendor's evaluation kit artwork, and incorporating the
>>artwork into the >>rest of our design. >>>>It turns out that this
evaluation kit is in PCI plug-in board format >>(clearly intended >>to run
ina desktop PC), and has the following stackup: >>>>TOP >>GND >>SIG1 >>GND
>>PWR >>PWR >>GND >>SIG2 >>GND >>BOT >>>>This is of course a wonderful
stackup for power distribution, but it >>requires running >>close to half of
the signals on the outside layers, since there are only two >>internal
>>signal layers. The evaluation kit runs many of the DDR SDRAM, PCI, and
GMII >>traces on >>the top and bottom layers. Only clocks and
HyperTransporttraces seem to be >>strictly >>limited to SIG1 and SIG2.
>>>>Myquestion is this: Is this kind of layout likely to radiate
significantly >>into other >>boards in the enclosure (relative to a board
with more layers, having added >>planes >>outside all signal layers),
therebyrisking excessive CM currents from the >>cables >>leading from these
other boards? As I have mentioned, we have always >>believed that it
>>would, and have avoided such a stackup. But I wonder if we've been going
>>overboard and >>wasting money on extra layers. >>>>Ken Hayden >>Consulting
Engineer >>Integral Access
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