[SI-LIST] Re: Pcie PLL bandwidth

  • From: "Chen, Sherman" <sherman.chen@xxxxxxx>
  • To: "balaseven@xxxxxxxxx" <balaseven@xxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
  • Date: Mon, 16 Jun 2014 14:59:16 +0000

Bala,

Looks CPU is sending jittery signal. You may need to check with your ASIC 
vendor what BW is used in the receiver PLL then you should apply the same BW in 
scope PLL, or constant freq. 

Best regards,

Sherman Chen 
Signal Integrity 
EMC Global Hardware Engineering
Tel: +86 21 60951100ext3329 

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of bala
Sent: Wednesday, June 11, 2014 2:25 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Pcie PLL bandwidth

Hello,
I am validating chip-chip pcie gen 1 interface.My design has pcie link between 
CPU<-->ASIC and CPU<-->FPGA.I set constant clock as my recovery clock in my TEK 
scope and eye was good when ASIC and FPGA driving my CPU.Whereas, eye was bad 
and too much jitter was observed at RX when CPU driving other two devices.I 
changed my clock from constant mean to PLL (
1.5 Mhz bandwidth as specified in the pcie spec) and got same output(eye was 
good) when ASIC and FPGA driving , interestingly eye was good at this time when 
CPU driving other two devices.Everything seems okay when PLL was chosen as my 
recovery clock.I know clock should be PLL for pcie compliance testing (min 1.5 
Mhz BW) as mentioned in the pcie specification.My question is why eye was good 
when other two devices driving my CPU in both the cases,whereas my eye was bad 
when constant clock was chosen and it was good when PLL was selected.
Regards
bala


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