[SI-LIST] Re: ddr3 Vtt sso issue
- From: Luping Liu <liewluping@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx, petebenjamin730@xxxxxxxxx, paul.taddonio@xxxxxxxxxxxxxx
- Date: Tue, 17 Jun 2014 14:13:34 +0800
Hi Pete:
I totally agree with Paul's suggestion,you should use a independent
regulator and use outer layer P/G plane pair to reduce the inductance of
the PDN loop in your case, and I have some additional comment for your
reference.
Consider the test setup you use,it is unavoidable to have large noise
on the VTT rail, you can reduce ,but can't eliminate the noise , cause we
have no such ideal PDN to offer such rush current. What we should really
care is the eye diagram of the signal,include the add/cmd/dq/clk, it should
be the final spec to decide if our VTT power design meet the requirement.
If you find problems in the ADD/CMD eye diagram too,them you can:
Besides N Paul's suggestions, addition 100uF bulk caps may be needed
to lower the noise.
Each VTT resistor should have a decap capacitor, 100n/1uF , 0402 size.
Again, route the VTT plane on top or bottom side( same size with your
regulator placement), with a GND adjacent.Inductance is important, so try
to reduce the distance between the voltage regulator and VTT resistor.
Increase the VTT resistor value, 39 ohm is not a good choice at this
case.
Reduce the current of the driver ,of add series resistor, based on
your simulation.
By the way , do we really need a all 0 to all 1 test pattern for the
address signal?
Regards,
LIU Luping
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