[SI-LIST] Re: ddr3 Vtt sso issue
- From: "Ghode, Nikhil" <Nikhil.Ghode@xxxxxxxxxxxxxx>
- To: "sherman.chen@xxxxxxx" <sherman.chen@xxxxxxx>, "dmarc-noreply@xxxxxxxxxxxxx" <dmarc-noreply@xxxxxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Mon, 16 Jun 2014 14:48:13 +0000
Pete,
Which processor/FPGA are you using? Also check VTT reference regulator
specification for current sink capability.
My DDR3 circuit also had VTT issue and it was due to current sink capability of
VTT regulator. I changed it and issue resolved.
-Nikhil
________________________________________
From: si-list-bounce@xxxxxxxxxxxxx [si-list-bounce@xxxxxxxxxxxxx] on behalf of
Chen, Sherman [sherman.chen@xxxxxxx]
Sent: Monday, June 16, 2014 10:32 AM
To: dmarc-noreply@xxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: ddr3 Vtt sso issue
Hi Pete,
Some thoughts of mine:
1. since the Vtt surge also occurred when the addrs switch from 1 to 0, this
looks not likely to be the inability of sinking current at Vtt.
2. could it be due to that the whole DDR circuit is grounded very poorly? And
the ref GND for the measurement is a faraway from the DDR? Do you still see the
surge when measuring across the decap of Vtt?
Adding decap between Vtt and Vdd help stabilize Vtt level but in your case
since the surge is only positive such decap may not help much.
Best regards,
Sherman Chen
Signal Integrity
EMC Global Hardware Engineering
Tel: +86 21 60951100ext3329
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Pete Benjamin
Sent: Friday, June 13, 2014 8:35 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] ddr3 Vtt sso issue
In our test setup we measured a surge of up to 500mV on Vtt when all addresses
switch (qty = 20) from 0 to 1 or 1 to 0 at the same time. Net RAS is 0.38V
during low state but increases to Vref level when Vtt increases to around 1.2V.
The driver rise time is 1V/ns and has a 50 ohm series switching from 0V to
1.35V, address termination is 39 ohm to Vtt (0.675V). No decoupling caps on
Vtt on other side of terminations, caps (to Vss) are on bottom side of
testboard of the dram board (dram board is connected to test board with a low
inductance socket, 1nH per pin).
Has anyone experienced such a Vtt issue? Suggestion to debug would be greatly
appreciated. Can't pinpoint inductance origin (estimated at 1.7nH).
Any option beside adding decaps on Vtt by the terminations? Should we add caps
between Vtt and Vcc (I read the SI list discussion from June 2012)? How do I
calculate/estimate qty of caps and values?
I got a simulation model (with speed2000) and I can see the vtt noise but
nothing so far can reduce dramatically the issue even if I add a lot of caps at
Vtt term.
Thanks,
Pete
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