[SI-LIST] ddr3 Vtt sso issue
- From: "Pete Benjamin" <dmarc-noreply@xxxxxxxxxxxxx> (Redacted sender "petebenjamin730@xxxxxxxxx" for DMARC)
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 13 Jun 2014 05:34:55 -0700 (PDT)
In our test setup we measured a surge of up to 500mV on Vtt when all addresses
switch (qty = 20) from 0 to 1 or 1 to 0 at the same time. Net RAS is 0.38V
during low state but increases to Vref level when Vtt increases to around 1.2V.
The driver rise time is 1V/ns and has a 50 ohm series switching from 0V to
1.35V, address termination is 39 ohm to Vtt (0.675V). No decoupling caps on
Vtt on other side of terminations, caps (to Vss) are on bottom side of
testboard of the dram board (dram board is connected to test board with a low
inductance socket, 1nH per pin).
Has anyone experienced such a Vtt issue? Suggestion to debug would be greatly
appreciated. Can't pinpoint inductance origin (estimated at 1.7nH).
Any option beside adding decaps on Vtt by the terminations? Should we add caps
between Vtt and Vcc (I read the SI list discussion from June 2012)? How do I
calculate/estimate qty of caps and values?
I got a simulation model (with speed2000) and I can see the vtt noise but
nothing so far can reduce dramatically the issue even if I add a lot of caps at
Vtt term.
Thanks,
Pete
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