[SI-LIST] Re: Pcie PLL bandwidth
- From: Nathan JP <jpnathan@xxxxxxxxxxx>
- To: "balaseven@xxxxxxxxx" <balaseven@xxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 11 Jun 2014 02:32:46 +0530
Hi Bala,
PLL follows Low frequency Jitter and cancels High freq Jitter. The Jitter in
the data signal may be too fast to allow the PCIe PLL to follow it, hence the
eye looks better.
Constant clock based measurement gives better indication of the jitter issues
and hence the bad eye.
This could also indicate possible issue in PCIe Ref Clock source for the CPU
(internal PLL/external clock Buffer) or its related power noise.
Is there any difference in the PCIe Ref Clk configuration (like SSC, common
clk/local clk) between these devices (CPU & ASIC/FPGA)?
How are the Ref clocks distributed between each of these PCIe devices?
Regards,
Nathan JP
________________________________
From: bala<mailto:balaseven@xxxxxxxxx>
Sent: â10-â06-â2014 23:56
To: si-list@xxxxxxxxxxxxx<mailto:si-list@xxxxxxxxxxxxx>
Subject: [SI-LIST] Pcie PLL bandwidth
Hello,
I am validating chip-chip pcie gen 1 interface.My design has pcie link
between CPU<-->ASIC and CPU<-->FPGA.I set constant clock as my recovery
clock in my TEK scope and eye was good when ASIC and FPGA driving my
CPU.Whereas, eye was bad and too much jitter was observed at RX when CPU
driving other two devices.I changed my clock from constant mean to PLL (
1.5 Mhz bandwidth as specified in the pcie spec) and got same output(eye
was good) when ASIC and FPGA driving , interestingly eye was good at this
time when CPU driving other two devices.Everything seems okay when PLL was
chosen as my recovery clock.I know clock should be PLL for pcie compliance
testing (min 1.5 Mhz BW) as mentioned in the pcie specification.My question
is why eye was good when other two devices driving my CPU in both the
cases,whereas my eye was bad when constant clock was chosen and it was good
when PLL was selected.
Regards
bala
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