[SI-LIST] Pcie PLL bandwidth
- From: bala <balaseven@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 10 Jun 2014 23:55:17 +0530
Hello,
I am validating chip-chip pcie gen 1 interface.My design has pcie link
between CPU<-->ASIC and CPU<-->FPGA.I set constant clock as my recovery
clock in my TEK scope and eye was good when ASIC and FPGA driving my
CPU.Whereas, eye was bad and too much jitter was observed at RX when CPU
driving other two devices.I changed my clock from constant mean to PLL (
1.5 Mhz bandwidth as specified in the pcie spec) and got same output(eye
was good) when ASIC and FPGA driving , interestingly eye was good at this
time when CPU driving other two devices.Everything seems okay when PLL was
chosen as my recovery clock.I know clock should be PLL for pcie compliance
testing (min 1.5 Mhz BW) as mentioned in the pcie specification.My question
is why eye was good when other two devices driving my CPU in both the
cases,whereas my eye was bad when constant clock was chosen and it was good
when PLL was selected.
Regards
bala
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