[SI-LIST] Re: PDN related

  • From: "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
  • To: "Scooby Doo" <si.scooby@xxxxxxxxx>, "Lynne D. Green" <lgreen22@xxxxxxxxxxxxxx>
  • Date: Mon, 15 Mar 2010 10:58:13 -0700

There are several good books on the subject.  Buy one and read it!  Or take
one of the good classes on the topic.  Don't expect to get your engineering
done on this site- and use your real name unless you really are a cartoon
dog.


> [Original Message]
> From: Scooby Doo <si.scooby@xxxxxxxxx>
> To: Lynne D. Green <lgreen22@xxxxxxxxxxxxxx>
> Cc: SI LIST <si-list@xxxxxxxxxxxxx>
> Date: 3/15/2010 10:42:18 AM
> Subject: [SI-LIST] Re: PDN related
>
> Hi Lynne,
>  
> This is what exactly what is wanted to ask. If the slew rate is 1v/ns,
then my 0.1uF capacitor value (designers blindly using value) will not
support due to existance inductive nature at that frequency.
>  
>  
> So kindly give some reference / notes so that choosing right value.
>  
>  
>  
>
> --- On Mon, 3/15/10, Lynne D. Green <lgreen22@xxxxxxxxxxxxxx> wrote:
>
>
> From: Lynne D. Green <lgreen22@xxxxxxxxxxxxxx>
> Subject: [SI-LIST] Re: PDN related
> To: "Scooby Doo" <si.scooby@xxxxxxxxx>
> Cc: "SI LIST" <si-list@xxxxxxxxxxxxx>
> Date: Monday, March 15, 2010, 5:20 PM
>
>
> Depends on the frequency range where you need PDN clean.
> If it is a wide range (generally true) then one would use
> more than one value of capacitor.  Remember, capacitor
> impedance increases at high frequency due to inductive
> package effects.
>
> Lynne
>
>
> "IBIS training when you need it, where you need it."
>
> Dr. Lynne Green
> Green Streak Programs
> http://www.greenstreakprograms.com
> 425-788-0412
> lgreen22@xxxxxxxxxxxxxx
>
>
> Scooby Doo wrote:
> > Hi SI Experts,
> >  
> >  
> > I have a question reg PDN.
> >  
> > Suppose an FPGA has 100 I/O pins with 10 VCCO/Gnd pairs. So an average
of 10 I/O pins for 1 VCCO/Gnd pair. Assume each I/O pin driving 10pf load.
> >  
> > My qn is, to make the clean PDN, is it enough to provide 100pf of
capacitor to each Vcc/Gnd pair?
> >  
> > I am not convinced with blindly provinding 0.1uF cap to Vcco pins.
> >  
> > kindly clarify.
> >  
> > Thanks in advance for your valuable feedback.
> >  
> > Rajesh
> >
> >   
>
>
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