[SI-LIST] PDN related
- From: Scooby Doo <si.scooby@xxxxxxxxx>
- To: SI LIST <si-list@xxxxxxxxxxxxx>
- Date: Mon, 15 Mar 2010 07:54:10 -0700 (PDT)
Hi SI Experts,
I have a question reg PDN.
Suppose an FPGA has 100 I/O pins with 10 VCCO/Gnd pairs. So an average of 10
I/O pins for 1 VCCO/Gnd pair. Assume each I/O pin driving 10pf load.
My qn is, to make the clean PDN, is it enough to provide 100pf of capacitor to
each Vcc/Gnd pair?
I am not convinced with blindly provinding 0.1uF cap to Vcco pins.
kindly clarify.
Thanks in advance for your valuable feedback.
Rajesh
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