[SI-LIST] Re: PDN related

  • From: "Brad Brim" <bradb@xxxxxxxxxxx>
  • To: "'Lynne D. Green'" <lgreen22@xxxxxxxxxxxxxx>, "'steve weir'" <weirsi@xxxxxxxxxx>
  • Date: Mon, 15 Mar 2010 19:52:52 -0700

hi Lynne,

I am an advocate of using a variety of decap values and have seen many
boards where doing so yields a more broadband low impedance with fewer caps
and lower cost. To qualify - most of the designs I simulated have generic
2-terminal MLCCs, not multi-pin ultra-low ESL caps.

I agree with everything you say except for one small detail. You cite
"several decades", which may be a little aggressive. Recall that decaps
operate as series LC resonators. L is the sum of device and cap mounting
inductance, spreading inductance from device to decap and ESL of the cap.
This low impedance resonance is defined by 1/sqrt(LC)/(2*PI). If you use
caps over a range of 0.01uF to 1uF the sqrt() will imply only one additional
decade of bandwidth. If you assume your loop inductances will vary by 10X or
so, then you may get another half decade of bandwidth. Of course, you can
use an even larger decap range but it's not common, or you can tweak on the
bulk caps a bit to extend this broadband behavior down another decade or
more. In practice your multiple values of decaps won't give you more than 2
decades of additional bandwidth for your target impedance. This sqrt()
bandwidth reduction means you may be required to use decaps in-package where
the inductance can be made less and you can use smaller valued decaps,
extending at most another decade but usually less. Then, on-chip caps have
very little loop inductance and can cover the higher frequencies.

As pointed out earlier, you can use an intentionally high ESR to make
lower-Q resonances in an effort to gain bandwidth. The same bandwidth you
can get with multi-valued caps is tough to get with a single value of cap,
even with many more caps.

I have seen a number of boards implemented with only 0.1uF caps that were in
production and worked well. One example I optimized started out with 400
0.1uF decaps and several bulk caps. I left the bulk caps alone but used
steps of (1, 2.2, 4.7) from 0.01uF to 1.0uF and was able to get
significantly better performance with less than half the decaps. This type
of result is not uncommon. I tried to use high ESR caps and only got
incrementally better bandwidth than the original design with all 400 decaps
placed. Of course, with my multi-valued decaps I did not get nearly so low
impedance as in the "big V" of the original design - but I figured 0.3mOhm
was overkill for my estimated requirement of about 10mOhm.

 -Brad Brim

> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx 
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Lynne D. Green
> Sent: Monday, March 15, 2010 7:09 PM
> To: steve weir
> Cc: Scooby Doo; SI LIST
> Subject: [SI-LIST] Re: PDN related
> Hi, Steve and Rajesh,
> Enough caps of one size will work, until your signal content 
> goes too far past the resonance frequency.
> And yes, different packages have different parasitics and 
> different resonance freqs.
> Using a variety of (carefully selected) caps covers a wider 
> frequency range (several decades).
> At the same time, this reduces the total number of caps 
> needed, and quite possibly total cost.
> These days, there are EDA tools to make this easier.
> And I agree wholeheartedly with Lee that there are plenty of 
> good books out there.  Istvan Novak's home page lists several 
> of them.  http://www.electrical-integrity.com/
> Lynne
> steve weir wrote:
> > And yet there are any number of boards and systems that have been 
> > built using mostly one capacitor value such as 0.1uF that work fine.
> >
> > Steve.
> >
> > Scooby Doo wrote:
> >> Hi Lynne,
> >>  
> >> This is what exactly what is wanted to ask. If the slew rate is 
> >> 1v/ns, then my 0.1uF capacitor value (designers blindly 
> using value) 
> >> will not support due to existance inductive nature at that 
> frequency.
> >>  
> >>  
> >> So kindly give some reference / notes so that choosing right value.
> >>  
> >>  
> >>  
> >>
> >> --- On Mon, 3/15/10, Lynne D. Green 
> <lgreen22@xxxxxxxxxxxxxx> wrote:
> >>
> >>
> >> From: Lynne D. Green <lgreen22@xxxxxxxxxxxxxx>
> >> Subject: [SI-LIST] Re: PDN related
> >> To: "Scooby Doo" <si.scooby@xxxxxxxxx>
> >> Cc: "SI LIST" <si-list@xxxxxxxxxxxxx>
> >> Date: Monday, March 15, 2010, 5:20 PM
> >>
> >>
> >> Depends on the frequency range where you need PDN clean.
> >> If it is a wide range (generally true) then one would use 
> more than 
> >> one value of capacitor.  Remember, capacitor impedance 
> increases at 
> >> high frequency due to inductive package effects.
> >>
> >> Lynne
> >>
> >>
> >> "IBIS training when you need it, where you need it."
> >>
> >> Dr. Lynne Green
> >> Green Streak Programs
> >> http://www.greenstreakprograms.com
> >> 425-788-0412
> >> lgreen22@xxxxxxxxxxxxxx
> >>
> >>
> >> Scooby Doo wrote:
> >>  
> >>> Hi SI Experts,
> >>>     I have a question reg PDN.
> >>>   Suppose an FPGA has 100 I/O pins with 10 VCCO/Gnd pairs. So an 
> >>> average of 10 I/O pins for 1 VCCO/Gnd pair. Assume each I/O pin 
> >>> driving 10pf load.
> >>>   My qn is, to make the clean PDN, is it enough to 
> provide 100pf of 
> >>> capacitor to each Vcc/Gnd pair?
> >>>   I am not convinced with blindly provinding 0.1uF cap to 
> Vcco pins.
> >>>   kindly clarify.
> >>>   Thanks in advance for your valuable feedback.
> >>>   Rajesh

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