[SI-LIST] Re: Looking for good source of information regarding Via tuning
- From: "bhuvana" <bhuvana.palanisamy@xxxxxxxxxxxx>
- To: "Tatsuji Sakurai" <weissbierjp@xxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Tue, 15 Jul 2008 16:23:17 +0530
Hi Tatsuji,
As data-communication speeds increase beyond 3 Gbps, signal integrity
becomes crucial for successful data transmission. Board designers try to
eliminate every impedance mismatch along the high-speed signal path, because
those discontinuities generate jitter and decrease the data eye openingâ??not
only reducing the maximum possible distance of data transmission, but also
minimizing the margin to common jitter specifications, such as SONET
(synchronous optical network) or XAUI (10-Gigabit attachment-unit
interface).
Due to the increasing signal density on pc boards, more signal layers are
necessary, and transitions with layer interconnects (vias) become
unavoidable. In the past, vias represented a significant source of signal
distortion, because their impedance is usually around 25 to 35Ω. This large
impedance discontinuity can reduce the data eye opening by as much as 3 dB
and can create a significant amount of jitter depending on the data rate. As
a result, board designers have either tried to avoid vias on the high-speed
lines or implemented new techniques, such as counter boring or blind vias.
Those methods help but add complexity and greatly increase board cost.
You can eliminate the significant impedance mismatch of standard vias with a
new "coaxlike" via structure. This structure places ground vias around the
signal via in a special configuration. Vias designed with this technique
show an impedance discontinuity of less than 4% (50±2Ω) on a TDR
(time-domain-reflectometry) plot and improved signal quality. This new
approach creates a vertical channel with a tunable impedance. Developers
created the via structure using a simple coax model with the signal wire in
the center; the surrounding ground shield builds a homogeneously distributed
impedance. Four ground vias, which align in a ring around the signal via in
the center, replace the uniform ground shield (Figure 1). Because these
outer vias connect to the pc-board ground or VDD (supply), they carry a
charge, and a capacitance builds between each of them and the signal via.
The calculated capacitances depend on the via diameters, the dielectric
constant, and the distance between the signal and ground via. The clearance
(antipad) of the center via "touches" the outer vias so that the capacitance
is homogeneous along the vertical channelâ??preventing a dramatic capacitance
increase at every power and ground plane. The ground vias on the outside
provide the path for the signal-return current and form an inductance loop
between signal and ground vias.
You can calculate the capacitance and inductance formed by one ground via
and the signal via with simple formulas (Reference 1). For the calculation,
you can assume that the two vias are essentially two wires of equal
diameters. D is the center-to-center distance between the signal and the
ground via, and a is the radius of the via. The inductance, L, of one via
pair calculates to:
The capacitance C calculates to:
EQUATION 1
Because the vertical channel, mainly formed by the five vias, is
homogeneous, the impedance Z calculates to:
Equation 1 calculates the capacitance in a standard two-wire system. The
improved via structure adds three more ground vias so that the amount of
positive charges in the signal via stays the same, but all the negative
charges distribute evenly among the four ground vias. Therefore, the overall
capacitance of the improved via structure is about the same as that of a
two-wire system. However, the inductance of this via model is one-quarter of
the inductance of a two-wire system, because four parallel inductance loops
form between the signal and the four ground vias, resulting in via impedance
Z:
Experimenters tested this via structure using FR4 polyclad 370, Getec, and
Rogers board materials on pc boards varying from 60 mils and six layers
thick to 130 mils and 16 layers thick. They verified the calculated via
impedance with TDR measurements and a 3-D field solver from CST (Computer
Simulation Technology). The formulas they derived predict the impedance
exceptionally well (±2Ω), regardless of the board thickness, because the
formula for the via impedance is independent of the board thickness. Table 1
compares calculated impedances for a six-layer, 62-mil FR4 test board
(er=4.1) with the TDR measurement results and simulated impedance values
from the Microwave Studio 3-D field solver from CST. The calculated via
impedances are within 2Ω of the measured results.
A TDR plot is a good method for determining the impedance of vias or other
discontinuities on a signal channel. Figure 2 shows the TDR plot measured on
two almost-identical channels of the test board. The only difference is that
one channel has a regular via with a diameter of 14.5 mils and an antipad
(clearance) of 10 mils, and the other channel has the improved via structure
with via diameters of 14.5 mils and center-to-center distances of 41 mils.
The TDR plot shows that the impedance mismatch of the SMA connector is the
same in both cases. The controlled-impedance via has an impedance of about
52Ω, and the impedance of the regular via is 48 to 54Ω. The impedance match
of the regular via is worse than that of the via structure. However, for a
regular via, the match is good, and, according to this plot, you should
expect little signal distortion.
One disadvantage of the TDR measurement is that the results are relative to
the rise time of the equipment. It does not show the frequency response of
the discontinuity for discrete frequencies. A better way to demonstrate and
compare the impedance mismatch of the vias is to look at the S21 scatter
parameter on a network analyzer (Figure 3). A plot of the S21 shows how
specific frequencies of the signal pass through the transmission-line
channel and how others get reflected or attenuated. Figure 3 shows the S21
plot of the two channels in the TDR measurement. They are identical, except
that one channel has the via structure (green curve), and the other channel
has a regular via (yellow curve). The via structure shows an exceptional
frequency response, and the first resonances are visible at about 10 GHz.
The regular via, on the other hand, shows multiple reflections over the
entire frequency band, even though the impedance mismatch is small. These
reflections cause certain frequencies of a signal to be more attenuated than
others, thus further degrading the high-speed signal.
On this test board (Figure 4), the distance between the SMA connectors and
the via is about 1.4 in., which equates to a frequency of about 2.35 GHz
(using Equation 2) that is clearly visible in the S21 plot. Although the
frequency response of discontinuities for an asymmetrical channel may differ
slightly, the channels are designed to be symmetric. The
signal-return-current path mainly causes the other reflections on the
yellow, regular-via curve.
Because the regular via provides no path for the signal-return current, the
current takes the least inductive path closest to the regular via. The
signal-return current flows through the ground vias of the SMA connector and
through the ground-via structure of the adjacent channel. Because the return
current takes the closest path, resonance frequencies in the S21 plot are,
as you would expect, at about 5 GHz (0.7 in.) and not at 4.2 GHz (0.8 in.).
Furthermore, the return current flows from the ground vias of that SMA to
the far-end SMA connector (an approximately 1.6-in.-long current path),
causing another resonance at about 2 GHz (equations 3 and 4). You can
clearly observe both phenomena, which the return current causes, in the S21
plot.
The following equations calculate the resonance frequencies of the channel
with the regular via:
EQUATION 2
EQUATION 3
EQUATION 4
The first conclusion you can draw from the S21 measurement is that the
resonance frequency depends greatly on the location of the discontinuity on
the transmission line. This statement does not imply that you should place
the via close to the transmitter or connector so that the impedance mismatch
appears at frequencies greater than 10 GHz. Unfortunately, in practice, this
approach would work only if there were a perfect impedance match at the
receiver. Otherwise, a reflection would appear at the receiver, and another
reflection would appear at the via closest to the transmitter. These
reflections result in a lengthy distance from receiver to via to receiver,
which again translates to a low resonance frequency.
The second S21 measurement conclusion is that the signal-return current
contributes a considerable amount of reflection. The S21 measurement in
Figure 3 shows two almost-identical channels that differ only in their
signal-return path and a slightly different impedance mismatch. The S21 plot
shows more reflections at the absence of this close return path for the
regular via because the signal-return current takes the closest, least
inductive path available, even if it is an inch away, thereby causing
resonances.
The signal-return current could flow through the inner-plane capacitance of
adjacent power and ground planes, but that capacitance is usually so small
that only high frequencies can pass. In most cases, the signal-return
current flows through the closest via that connects the reference layers of
the signal trace. Those return-current vias can be far from the actual
signal via (Figure 5). To demonstrate this effect, experimenters placed a
ground via approximately 100 mils from the regular via and plotted the
current density in a controlled-impedance via (Figure 5a) with the current
density for the structure (Figure 5b). It is clear that most of the return
current flows through the added ground via some distance away. This extra
distance for the return current causes reflections that appear in the S21
plot.
The impact of broadband reflections becomes more visible when you examine a
real data signal with a wide frequency spectrum, such as a PRBS
(pseudorandom-bit-stream) pattern. To illustrate this impact, experimenters
sent a 27â??1 PRBS pattern at 3.125 Gbps through both channels and recorded
the output waveforms (Figure 6). The channels are only 2.8 in. long, but the
impact of the vias is clearly visible. The regular via (yellow curve)
attenuates multiple frequencies, resulting in a smaller data eye and a
slower rise time than a controlled-impedance via (green curve).
Finally, the impedance mismatch should be as small as possible. Even the
smallest mismatch shows up at one discrete frequency on the S21 plot and
impact the signal quality. You can maximize the performance of
controlled-impedance vias by following important design parameters, such as
spacing, trace widths, and pad widths. For example, the antipad, or
clearance size, of the signal via is critical. It must be at least the
difference of distance between signal and ground via, a, and the via
diameter, D, so that the signal-via antipad touches the ground via.
Otherwise, the metal on the ground, power layer, or both comes too close to
the signal via and creates additional unwanted capacitance thereby reducing
the via impedance to less than the calculated 50Ω.
Likewise, every via that connects a microstrip line on the top or the bottom
layer with a stripline on an inner layer creates a stub. When the stub
length is smaller than the signal rise time, the stub is barely noticeable.
If the stub length is longer, it can cause considerable signal distortion.
For example, a stub of 40 mils has a run length of about 14 psec in a system
with a 3.125-Gbps signal with a rise time of approximately 50 psec. In the
worst case, the stub length is a quarter- wavelength of an important
frequency, and the stub becomes a short circuit for that frequency,
canceling out the original signal.
The above equations assume that the diameter is the same for the signal and
the ground vias. To use different diameters, you need to modify the formula
for the capacitance. Designers should choose the via diameters according to
the width of the connected traces. If the trace is much smaller than the
via, the transition from the 50Ω trace to the via pad causes an unwanted
discontinuity. Designers should also consider the distance between the
ground vias and the connected trace. It can become an issue when the
separation between the ground via and the trace is smaller than the distance
between the trace and the reference layer, creating additional capacitance
for the trace and again dropping the trace impedance to less than 50Ω. On
the test board, for example, the distance between the signal trace and the
ground vias is about 11 mils, and the trace is about 10 mils above the
ground-reference layer.
Another important design consideration is pad size, because every via that
connects to a trace requires a pad. This pad should be as small as possible,
because the distance from the pad to the ground vias is smaller than the
distance from the signal via to the ground vias. A shorter distance results,
due to the pads, and increases the capacitance, which reduces the overall
impedance.
In a typical design, four ground vias are not always available. The via
structure works equally well with power vias as long as the return current
has a path from VDD to ground through a nearby bypass capacitor.
For example, consider boards that contain this via structure inside a BGA
pinout with a 1-mm grid. Because of the fixed pinout, you may connect only
two outer vias to ground; you connect the other two vias to VDD. The via
structure works well because you can also place SMD bypass capacitors
between VDD and ground inside the BGA.
You can also use the via structure for differential signals. The signals can
share the two outer vias, saving board space. Texas Instruments uses this
method on the evaluation boards for its XAUI transceivers, which offer
limited space inside the BGA. For controlled-impedance vias, the size of the
layer separation does not matter, because the ground vias and not the metal
layers form the capacitance. Regular vias, however, depend on the
capacitance from the layers. Therefore, you must design them specifically
for different layer stackups even if the board thickness does not change.
P.Bhuvana
PCB Design Engineer
Tessolve Services Pvt Ltd,
Plot No.31 (P2), Electronic City Phase II
Bangalore, 560 100
Tel : +91-80-4181 2626
Fax : +91-80-4120 2626
Cell: +91 9741187622
----- Original Message -----
From: "Tatsuji Sakurai" <weissbierjp@xxxxxxxxxxx>
To: <si-list@xxxxxxxxxxxxx>
Sent: Tuesday, July 15, 2008 3:31 PM
Subject: [SI-LIST] Re: Looking for good source of information regarding Via
tuning
Hello,
This article "controlled impedance vias" was looked very
interesting, however I have failed at the early stage of
this article. I just simply did not understand "arc-cosh
(D/2a)" where D is diameter of via, 2 is via pitch between
sig via and GND via. If I apply typical design rule to
this formula, D/2a would be value less than 1. To make
this number more than 1, the design would be unlikely, I
think.
How do I understand this formula? Or imaginary number
would be accepted in the arccosh?
Can somebody explain?
- Tatsuji
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of todd t
Sent: Thursday, July 03, 2008 8:21 AM
To: Denomme, Paul S.
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Looking for good source of
information regarding Via tuning
Paul, perhaps this article is of interest to you:
http://www.edn.com/index.asp?layout=article&articleid=CA324403
"designing controlled impedance vias", by tommy neu, TI.
not a replacement for a tried and true simulation study
with a 3d field solver, but you'll be more familiar with
what you're after and a general direction on how to get
there.
ciao,
-todd t
-mantaro networks
On Jul 2, 2008, at 1:55 PM, Denomme, Paul S. wrote:
> Hi All,
>
>
> I have a customer that is looking for
assistance in
> providing Via tuning. Basically they are looking to
minimize the
> impact
> their via's have on their high speed signals. I am
familiar with the
> various techniques to minimize the impact a via has on
the signal
> integrity ( ie minimize pad size, maximize anti pad,
remove NFP's,
> backdrilling, etc) but is their any good source of
information on
> how to
> tune a via to a particular impedance? What about
software? I'm
> familiar
> with the 3D field solvers, but is their any reasonably
priced software
> available that will support this type of work? Any
assistance on this
> issue would be greatly appreciated.
>
>
>
> Thank you
>
>
>
> Paul Denomme
>
> Viasystems
>
>
>
>
>
>
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--
=todd=
"be who you are and say what you feel, for those who mind,
don't
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