[SI-LIST] Re: Layer Stackup
- From: "Steven M. Waldstein" <swldstn@xxxxxxxxxxxx>
- To: "Michael Khusid" <mkhusid@xxxxxxxxxx>
- Date: Mon, 12 Jan 2004 20:36:06 -0500
Mike,
Its a typical host bridge application with processor
busses, memory busses, PCI-X, GigE GMII, etc. Top speeds
are, at or about 533MHz-666MHz.
We typically assume there has to be sufficient decoupling
that is well designed to deal with power supply impedance so
we tend to favor keeping all signals reference to the same
plane without relying on strategically located capacitors
to provide the return path. I would think this would be
better for board routers. Are their any board router
that understand where to put decoupling if it provides
the return path?
We assume internal signal layers are 0.5 oz. and power
planes are 1 oz. Top and bottom layers of 0.5 oz platted
up to ~1-2 oz are typical.
Any further thoughts are appreciated.
Steve
swldstn@xxxxxxxxxxxx
-----Original Message-----
From: Michael Khusid [mailto:mkhusid@xxxxxxxxxx]
Sent: Monday, January 12, 2004 10:36 AM
To: swldstn@xxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: Layer Stackup
Steve,
There are two effects in play here. Both need to be considered when
examining stackups.
1. Return path discontinuity when signal changes layers - return current
needs to jump from power to ground through a decoupling capacitor, or from
ground to ground layer through a ground via.
2. Impedance of power/ground structure -- the distributed capacitance
between power and ground in terms of plane-to-plane capacitance plus
decoupling capacitors placed on the board.
The stackup #1 addresses issue #1 and ignores issue #2.
Vice versa, the stackup #2 addresses issue #2 for PWR1 and ignores issue #1.
Given little knowledge of the layer thicknesses and the application, I think
these stackups are equal. You will need to worry about quality decoupling
capacitor scheme in either case.
Mike
----------------------------------------------------------------
Michael Khusid
Ansoft Corporation
SI/HF Application Engineer
25 Burlington Mall Road, 5th floor
Burlington, MA 01803-4100
Tel 781-229-8900 Ext. 134
Fax 781-229-8624
---------------------http://www.ansoft.com ---------------------
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Steven M. Waldstein
> Sent: Friday, January 09, 2004 10:09 PM
> To: calixlnguyen@xxxxxxxxxxx; chris.mcgrath@xxxxxxxx; si-
> list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Layer Stackup
>
> I have a follow up question.
>
> My experience with other is that they prefer a stackup
> more like
>
> Signal
> Ground
> Signal
> Pwr 1
> Pwr 2
> Signal
> Ground
> Signal
>
> This is only an 8 layer example but I've been told they prefer
> this to
> Signal
> Ground
> Signal
> Pwr 1
> Ground
> Signal
> Pwr 2
> Signal
>
> Because all signals are uniformly reference to ground. And a signal
> that has to go in both x and y stays reference to the same ground
> plane. They prefer this and don't have to rely on local decoupling
> when a signal changes layer to give the propeper return path.
>
> Any comments about this or feedback.
>
> Steve
> swldstn@xxxxxxxxxxxx
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Long Nguyen
> Sent: Friday, January 09, 2004 1:50 AM
> To: chris.mcgrath@xxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Layer Stackup
>
>
> I agree. Having interplane capactance between power and ground planes
> also
> provides another advantage is that you may be able to use thinner ZBC
> cores
> with 2mils thickness instead of 3mils and thus reducing your overall board
> thickness. In other words, you get 'free' buried capacitance for your
> stackup at no additional charge.
> -Long
>
>
>
> ----- Original Message -----
> From: "Chris McGrath" <chris.mcgrath@xxxxxxxx>
> To: <si-list@xxxxxxxxxxxxx>
> Sent: Wednesday, January 07, 2004 8:23 AM
> Subject: [SI-LIST] Re: Layer Stackup
>
>
> > David,
> >
> > Just out of curiosity, why are you going to Nelco 4000-13? From your
> > original post it doesn't sound like you are overly concerned about
> > routing lengths and you are not dealing with excessively high speed
> > signals.
> >
> > Regarding Lee's post, I think it is good practice to have at least one
> > pair of power and ground planes next to each other but having worked on
> > a 42 layer board (Nelco 4000-13SI, 4 mils) that had interfaces running
> > between 125 MHz and up to 1 GHz and routing it completely in a dual
> > stripline stackup without any adjacent power and ground planes I think
> > that proper coupling of the planes can be achieved without forcing you
> > to muck with your proposed stackup. I should add that the 42 layer
> > board carried a range of voltages including 0.9V from a daughter board
> > (through connectors) and had no problems passing the EMI qualifications.
> > Nothing involved with that board was easy, but it showed that what you
> > are proposing can be done.
> >
> > -Chris
> >
> >
> > > -----Original Message-----
> > > From: Lee Ritchey [mailto:leeritchey@xxxxxxxxxxxxx]=20
> > > Sent: Wednesday, January 07, 2004 11:03 AM
> > > To: david.kaushansky@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> > > Subject: [SI-LIST] Re: Layer Stackup
> > >=20
> > >=20
> > > David,
> > >=20
> > > The problem you will have with this stackup is the lack of=20
> > > interplane capacitance between power and ground planes. This=20
> > > will manifest itself in several ways. Very high ripple on=20
> > > your power supplies when transmission lines switch, =20
> > > potentially very high EMI, unstable operation.
> > >=20
> > > It is imperative that you make sure that Vcc and ground=20
> > > planes are close to each other. If you have several=20
> > > different supply voltages, this will mean several pairs of=20
> > > power planes.
> > >=20
> > > If you really need that many signal layers, it will be=20
> > > necessary to add plane layers to get it right.
> > >=20
> > > Lee=20
> > >=20
> > >=20
> > > > [Original Message]
> > > > From: <david.kaushansky@xxxxxxxxxxxx>
> > > > To: <si-list@xxxxxxxxxxxxx>
> > > > Date: 1/7/2004 6:40:52 AM
> > > > Subject: [SI-LIST] Layer Stackup
> > > >
> > > > The design I am working has a fairly dense placement. To=20
> > > try minimize=20
> > > > my
> > > > time in artwork, I would like to add as many routing layers=20
> > > as possible
> > > to=20
> > > > my layer stackup. I was thinking of using an 18 layer board of Nelco
> > > > 4000-13, with the following stackup:
> > > > Signal1
> > > > GND
> > > > Signal2
> > > > Signal3
> > > > PWR
> > > > Signal4
> > > > Signal5
> > > > GND
> > > > Signal6
> > > > Signal7
> > > > GND
> > > > Signal8
> > > > Signal9
> > > > PWR
> > > > Signal10
> > > > Signal11
> > > > GND
> > > > Signal12
> > > >
> > > > The skinniest dielectric thickness is 4 mils, all signal layers
> are=20
> > > > 0.5
> > > Oz=20
> > > > copper and plane layers are 1 Oz copper. The fastest signals are=20
> > > > 100MHz,
> > > > with rise times in 500ps range.=20
> > > > My primary concern is the ratio of 6:12 of plane layers to signal
> > > layers.=20
> > > > I usually try to design for a ratio of about 8:10 or 9:9. I know
> I=20
> > > > will
> > > > have to be very careful about crosstalk on adjacent layers,=20
> > > but other
> > > than=20
> > > > that, what else should I be concerned about?
> > > >
> > > > Thanks
> > > > Dave
> > > >
> > > >
> > > >
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