[SI-LIST] Re: Intel Motherboard with DDR2
- From: steve weir <weirsi@xxxxxxxxxx>
- To: gtang@xxxxxxxx, <Chris.Cheng@xxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 17 Feb 2005 02:38:22 -0800
George, I have to agree with Chris Cheng on this one, which also touches
back on the subject of the AR resonance between the bypass caps and power /
gnd cavity, and pwr / gnd cavity resonances.
If we use the layout suggested, then L1/L3/L6/L8, are adjacent GND If we
make the spacing from L3/L4, and L5/L6 big, then the two power layers will
have very little impact on any of the TX lines. And if the IC mfg. was
smart enough to reference all of their fast I/Os to gnd, then we have a
nice smooth transmission line for each signal out of the package onto the
PCB. No muss, no fuss.
As to core power, the device package forms a low pass filter that welding
the planes together will not overcome.
So, finally, we have the I/O power. The I/O power pins have the same
inductance limitations as the core power pins. If the chip mfg fails to
supply enough capacitance inside the package, the I/O will starve, and
again welding the planes together, sic C-Ply, isn't going to help.
Now, if the IC mfg messes up, we will have insufficient capacitance inside
the package, or signals referenced "suboptimally".
First let's look at the power. By adding two more gnds in the middle of
this stackup, with thin dielectric we can make the power better, but not
great, due to via inductance. We could alternately rearrange the stack-up
for pwr/gnd near the top of the stackup and near the bootm, and still have
gnd referenced signaling on a 10 layer board:
S-G-P-S-G-G-S-P-G-S
C-Ply at L2/3, and for symmetry at 8/9 might rescue us from what is really
an IC design problem.
If the chip has some signals referenced to power, like DDR2 does, then this
layout would allow us to set the spacing to route those signals on L4, and 7.
If the chip fails to reference high speed I/Os or does so randomly, the
C-Ply may or may not be a big enough band-aid to make this work.
Steve
At 07:27 PM 2/16/2005 -0800, George Tang wrote:
>Chris,
>
>The power consumed by an IC can be divided into 2 categories: digital core
>logic power and I/O power. If your chip consumes mostly I/O power, then you
>would need to minimize the signal/return inductance. But if your chip
>consumes most of the power for the internal core logic and very little I/O
>power, then your priority shall be to lower the power/ground impedance in
>chip and on board. This memory module should consume mostly I/O power, so
>the PCB stackup is appropriately adjusted for this purpose.
>
>George
>
>
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Chris Cheng
>Sent: Wednesday, February 16, 2005 6:24 PM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Intel Motherboard with DDR2
>
>
>This looks like the stack up I came up with a few years ago on a different
>product.
>It allows the most number of routable high speed layers (all 4 of them).
>Easy EMI containment (stitch the edge with ground vias and you have a nice
>farady cage).
>If you follow my rant for the pass few years, I never believe in the need to
>have thin core or ultra low power plane impedance if you do your packaging
>and core decoupling right.
>Any reason why you are concern ?
>
>-----Original Message-----
>From: Jon Keeble [mailto:jkeeble@xxxxxxxxxxxx]
>Sent: Wednesday, February 16, 2005 5:23 PM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Intel Motherboard with DDR2
>
>
>Hi there, Layout Lovers.
>
>Page 21 of the Intel document making recommendations for a DDR2 motherboard
>(Lindenhurst)
>
>http://www.intel.com/idf/us/fall2003/presentations/F03USOSAS184_OS.pdf
>
>shows an 8 layer motherboard layup unlike anything I've seen suggested in
>this forum
>- S
>- GND (1 oz)
>- S
>- P (2 oz)
>- P (2 oz)
>- S
>- G (1 oz)
>- S
>
>I'm curious why Power and GND layers not paired.
>
>The only 'payoff' seems to be that all signal layers are adjacent to GND
>layers, so P would presumably be quiet.
>
>Comments?
>
>Regards
>
>Jon
>*************
>Jon Keeble
>JKC
>Unit 1, 1 Roger Street
>Brookvale, NSW 2119
>Australia
>PHO +61 -2 9484 6453
>MOB +61 407 842 840
>
>
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