[SI-LIST] Re: Intel Motherboard with DDR2
- From: Ray Anderson <ray.anderson@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 17 Feb 2005 09:21:59 -0800
Geoff Stokes wrote:
>Hi Chris and Steve
>
>With interest in smaller packages I have a question. Chris's "100 MHz" rule
>seems to apply for digital processors and memory chips which come in fairly
>large packages, say 25 mm or more on a side. Small RF devices rely on
>decoupling at considerably higher frequencies, and if you change the
>decoupling, there is a major effect on performance at those same high
>frequencies. Do you find that the critical frequency (100 MHz) is variable,
>and would you not say that for smaller packages, the rule comes in at some
>higher frequency?
>
>Cheers
>Geoff
>
>
>
Geoff-
The "~100MHz" cutoff frequency is determined by the pwr/gnd loop
inductance of the package resonating with the capacitive load presented
by die. For typical processors I've seen this number range from about 70
MHz up to maybe 120 MHz.
Small packages can have a relatively high pwr/gnd loop inductance if
not designed properly. The capacitive load presented by smaller die will
presumably be smaller than a largish processor. Predicting the packaging
cutoff frequency by rules-of-thumb can be a dangerous thing to do, but I
would expect a smaller package with a well designed package PDN (i.e.
with low loop inductance) and a small die to have a somewhat higher
package resonance frequency (can't really say be how much without doing
a thorough analysis). The issues involved for I/O are somewhat different.
See the paper "Chip-Package Resonance in Core Power Supply Structures
for a High Power Microprocessor" by Smith, Roy and Anderson at the
following URL for a more detailed discussion of chip package resonance
as it applies for core power:
http://www.si-list.org/files/published/sun/asme_2001.pdf
Ray Anderson
Senior Signal Integrity Staff Engineer
Xilinx Inc.
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