[SI-LIST] Re: Intel Motherboard with DDR2

  • From: Steve Weir <weirsi@xxxxxxxxxx>
  • To: jkeeble@xxxxxxxxxxxx, <scott@xxxxxxxxxxxxx>, "silist" <si-list@xxxxxxxxxxxxx>
  • Date: Sun, 20 Feb 2005 20:21:21 -0800

At 09:12 AM 2/21/2005 +1100, Jon Keeble wrote:
>Scott said:
> > On DDR2 modules, all data, strobe and clock signals are referenced to
> > Ground.
>
>This is good; and now I understand that onchip bypassing makes it work.
>
> > And all address and control signals are referenced to Vddio.
> > This was done as a compromise to support high speed signaling of the
> > data bus, which has twice the frequency of the address/control bus.
>
>I assume the number of layers in the DDR2 module PCB is what governed this
>compromise.

Yes.

> > It is only necessary to maintain the integrity of the transmission line
> > through connectors and packages.  This is why DDR2 modules were designed
> > with ground referencing for the high speed data, strobe and clock
> > lines.  It is easy to maintain integrity of this path. If this is done,
> > no bypass is necessary at the sockets.
>
>Address/control inputs to the module only.
>However, they will (using the Intel stackup) see a break in return plane
>(from GND to Vddio) at the connector.
>
>Scott, are you saying that bypassing GND-Vddio at the socket would be
>ineffective in providing a 'bridge' at this point?

For high frequency the integrity is compromised by the discontinuity.  They 
get away with this because address and control are comparatively slow as is 
the cavity size on the RDIMMs.  But, it is an invitation to all of teh 
problems that we have discussed, including AR, and cavity resonance.

>Jon
>
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