[SI-LIST] Re: Intel Motherboard with DDR2
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: weirsi@xxxxxxxxxx
- Date: Fri, 18 Feb 2005 10:56:29 -0500
I whole heartedly agree with Steve.
I think people have trouble with our "heresy" because of the engineering
mindset of looking at return path with respect to the silicon. As I have
said many times previously, in controlling the return path you are
controlling mode conversion. There are four places I see where mode
conversion can occur.
* At the silicon/package boundary
* At the package/PCB boundary
* At the PCB layer transition boundary
* At the PCB connector boundary
Let's look at each one.
*
Silicon/Package Boundary*
As Chris Cheng, Steve Weir, and I have said many, many times, this area
is the responsiblity of the silicon and package designer. Since most
package traces are ground referenced, it is imperative that the correct
amount of on-die capacitance be applied to deal with Vcc and ground
return currents for driver signal transitions. With sub 200 ps driver
switching rates, there is nothing you're going to do with the printed
circuit board or bypass capacitors to fix this problem if it was
designed incorrectly.
Because of this, immaterial of whether the driver technology is CML,
CMOS, LVDS, RTL or whatever, what the silicon package boundary does is
to transform transistor switching energy into a well-defined wave down a
transmission line that is generally (but not always) referenced to
ground. If the designers do not do their job well, the result is noise
in the die and package. What leaves the package, however, is still a
wave propagating with a defined instantaneous AC reference. Which
brings us to the next boundary.
*Package/PCB Boundary*
At the package/pcb boundary, a signal on a transmission line with a
well-defined instantaneous reference path has to traverse the path from
package trace, to package vias, to package ball, to PCB pad, to PCB via
to PCB trace. This is actually a long and tortorous path where it is
important to keep keep the instantaneous return path intact. At any
point along the way, if the return path is broken, by a long path to
keep the package grounds and PCB grounds attached (for example, through
a poor package pinout with too few ground balls.) then part of that
return path energy will be mode converted into some other path,
generally injecting noise into something, as either crosstalk, EMI or
power noise.
The package designer is responsible for ground and power ball
placement. If a package is designed such that signals only reference
ground plane layers, then ground balls should be scattered throughout
the signal transition ball regions. However, if the package uses both
ground and vcc referenced trace layers, then the designer must provide
both ground and vcc balls throughout the signal ball region, in order to
maintain the return path and keep mode conversion from happening in the
package.
Now here is where it gets tricky. If the package traces are totally
ground referenced, and ample ground balls are placed in the signal ball
area to provide a good continuous return path, then it makes an
incredible amount of sense to continue this pattern throughout the PCB,
by transitioning signals from the package to ground referenced layers.
If you make a mistake and reference only one return path, and it is the
wrong one, then large amounts of transmission line energy will be mode
converted into parallel plate mode energy on the planes, which are
resonant cavities.
However, if the package was designed with ground and vcc referenced
trace layers, then you may not have the design information needed to
determine which return path to use. If you choose wrong, then a large
amount of energy will be mode converted and lost by power injection into
one of the interplane layers. This causes resonance, which as Steve
says, is very, very bad. So, if you want to be absolutely sure with
combination ground/vcc referenced package traces, you will use balanced
stripline construction with ground on one side and vcc on the other.
Voila, the return path is kept in tact at all times and the stripline
will help to ease the transition to blanced vcc/gnd return path.
To summarize:
* Transition to layer with wrong return path .... bad.
* Transition to layer with correct return path ... good.
*PCB Layer Transition Boundary*
At any point on the printed circuit board where a trace transitions from
one layer to another, there will be a change in reference planes. For
this to occur cleanly, two things must occur.
1. The same reference plane must be used on both layers.
2. The much be vias from plane to plane to "stitch" the return path
together as a signal transitions through a via.
Optimally, if you use ground referenced signaling, then extra ground
vias can be provided to stitch the planes together. For high frequency
RF-type low-loss transitions, I use a coaxial pattern of ground vias the
surround a central signal via. With this it is possible to pass through
a PCB with 30+ GHz of bandwidth. For lower bandwidth, this is not
necessary, but it is necessary to provide ground vias that are in the
near field of the signal transition vias, otherwise power will be
injected into the cavity, it will cause resonance and it will cause
crosstalk. Again, parallel plate mode conversion always happens. All
we can do is to limit the cavity size. This is best done with ground
stitched cavities.
If you use vcc referenced signaling, you run into the problem of
injecting unwanted energy into the power plane cavities. Since here are
generally not multiple power plane layers carrying the same voltage
(i.e. two 2.5 V planes) there is no nice way to stitch the planes
together with vias, like there is for ground planes. There are then only
two ways to reduce and contain high frequency resonances in the power
plane cavities:
1. Use bypass caps.
2. Make the planes small.
Bybass caps help the problem up to several hundred MHZ, but will have
absolutely no effect on sub 200ps switching I/O busses. They are
totally ineffective at I/O switching frequencies. The only other
solution is to make the planes smaller and push the resonant frequency
high enough so that no unwanted modes are excited. Unfortunately, this
is better said than done in most PCB designs. Which is why ground
referenced signaling and signal transtions are preferable on a PCB. At
least they can be contained by stitch vias and good return path control
vias. Why inject unwanted noise into the power system with Vcc
referenced signals when the ground referenced alternative has much lower
overall noise?
Now, I've gotten a bit tired of writing. However, as an exercise for the
student you should be able to follow the path back up the the receivng
chip, which ...oh by the way ... might just have a totally different set
of reference layers for signal traces than the driver package. Once you
go through this exercise, you will see that the lowest noise solution is
the ground referenced solution.
Quit thinking about what the driver does and start thinking what happens
along the transmision lines. If you keep the transmission lines
continuous from driver to receiver, then you will transfer maximum power
to the receiver and lowest noise to the power system and the universe.
Just say no to electromagnetic noise polution.
best regards,
scott
Scott McMorrow
Grand Poobah
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com
Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC
steve weir wrote:
>Alex, now there is an invitation I cannot resist: "Have rocks will
>travel!" Hopefully, they are not in my head.
>
>Well "suboptimal" was a term I consider diplomatic. Here are two words
>that summarize my grief with referencing against multiple voltage
>planes: cavity resonance.
>
>Given that if we "simply" maintain reference for any given signal against
>plane(s) of the same voltage, then the worst thing that we have to deal
>with is via design and stitch density. In the optimal case we never switch
>layers at all. In the next approximation, we run E-W on one side of a
>plane and N-S on the other. With the right via and antipad design, the
>transmission line sees virtually no impedance discontinuity. Going down in
>desirability, we run against planes of like voltage that are stitched
>together with vias at an appropriate density. In each of these cases our
>"coax" shields are at worst tied together with a series of small inductors
>in the form of the stitch vias. The cavities formed between the two
>shields can be made small, and therefore have very high SRFs that do not
>materially interfere with the return current in our signal spectrum.
>
>When we switch reference planes between two planes that operate at
>different voltages, the return current path has to find its way between
>those two planes "coax shields". It does so through a tortured combination
>of: displacement current, vias and the bypass capacitor network. That
>combination has a number of resonances that can all materially interfere
>with return currents over a wide band. To deal with these resonances we
>have limited tools at our disposal:
>
>At moderate frequencies we can use high ESR caps by hook or by
>crook. Larry and company have their well-known method for building a
>multi-pole bypass network that results in a higher ESR than the big "V" for
>a like impedance target. That helps lower the AR peak. Istvan's advocacy
>of specific, high ESR capacitors could with the right values of capacitor
>ESR be used to eliminate the AR peak entirely, whether designing with the
>big "V" or using the multi-pole method.
>
>But due to attachment inductance, cavity resonance control with bypass caps
>of any kind remains an elusive critter. A number of people have applied
>considerable thought and energy to the problem without yielding a clean,
>economical solution.
>
>The other tool in our arsenal is the use of exotic dielectric
>material. There is some really neat stuff out there like C-Ply. But that
>stuff isn't free. The high K materials have an advantage of both higher
>capacitance, which may be used to help with the AR resonance, and higher
>loss, which can be employed to help with cavity resonances. Aside from
>cost, high K material has other issues including some
>manufacturability. But the real danger of high K dielectric is that it can
>be misapplied in such a way that it undermines the PDS due to once again
>... cavity resonance.
>
>I am inclined to characterize any methodology that:
>
>1) Is much less likely to work under any circumstances, and
>2) Requires higher net cost niche components and/or materials
>
>suboptimal when compared to a methodology that works using ordinary low
>net-cost components and/or materials.
>
>
>Regards,
>
>Steve
>
>
>At 01:46 PM 2/18/2005 +0000, Gourari, Alexandre wrote:
>
>
>
>
>>I think that calling some solution suboptimal just because its technical
>>feasibility is a bit of a stretch. If a current "wants" to return through
>>VCC plane either on-die or on-board decoupling just helps to avoid broken or
>>completely missing (as in case with coax cable) VCC plane.
>>As to Chris's note on either current prefers Vterm or VDDQ it depends not on
>>where DC current bias flows but where receiver's and transmission line
>>capacitance is.
>>I got 2 models to review:
>>1. Very short transmission line, negligible capacitance to GND and VCC,
>>loaded by receiver with significant input-GND and input-VCC capacitance,
>>typical CMOS circuit. In that case GND and VCC planes equal in their
>>provision for return current.
>>2. Long transmission line with significant capacitance only to GND plane (or
>>coax shield), receiver's input-VCC capacitance is negligible. Returm current
>>flows through GND plane only, no need for return on VCC at all.
>>
>>Shoot back, I'll try to dodge... ;-)
>>
>>Best regards,
>>
>>Alex Gourari
>>
>>
>>
>>-----Original Message-----
>>From: steve weir [mailto:weirsi@xxxxxxxxxx]
>>Sent: Thursday, February 17, 2005 5:20 PM
>>To: jkeeble@xxxxxxxxxxxx; Chris.Cheng@xxxxxxxxxxxx;
>>si-list@xxxxxxxxxxxxx
>>Subject: [SI-LIST] Re: Intel Motherboard with DDR2
>>
>>
>>Jon,
>>
>>How close GND and power need to be depends on the power delivery impedance
>>and cut-off of the IC. Considering that the IC is a lot smaller than the
>>PCB, it "generally" ( beware generalizations ) makes more economic sense to
>>put package cost into the IC than the PCB. However, feasibility can raise
>>its ugly head in any particular circumstance to disprove the "general" rule
>>for that case.
>>At 08:59 AM 2/18/2005 +1100, Jon Keeble wrote:
>>
>>
>>>Chris Cheng said:
>>>
>>>
>>>
>>>>It allows the most number of routable high speed layers (all 4 of them).
>>>>Easy EMI containment (stitch the edge with ground vias and you have a
>>>>
>>>>
>>nice
>>
>>
>>>>farady cage).
>>>>... I never believe in the need to
>>>>have thin core or ultra low power plane impedance if you do your
>>>>
>>>>
>>packaging
>>
>>
>>>>and core decoupling right.
>>>>Any reason why you are concern ?
>>>>
>>>>
>>>This stack up challenges two of my long standing articles of faith:
>>>- closely spaced plane pairs
>>>- balanced cores (S-S or plane-plane)
>>>
>>>**
>>>
>>>George said
>>>
>>>
>>>
>>>>This memory module should consume mostly I/O power, so
>>>>the PCB stackup is appropriately adjusted for this purpose.
>>>>
>>>>
>>>The stackup is for the motherboard, not the DDR2 module.
>>>Pages 23,24,25,26 of the same article show the routing of each of the four
>>>layers.
>>>
>>>**
>>>I am currently looking to see if DDR2 specifies reference planes for each
>>>signal.
>>>Then, of course, the same signal / plane relationship should be used on the
>>>motherboard.
>>>
>>>
>>>Jon
>>>
>>>------------------------------------------------------------------
>>>To unsubscribe from si-list:
>>>si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
>>>
>>>or to administer your membership from a web page, go to:
>>>//www.freelists.org/webpage/si-list
>>>
>>>For help:
>>>si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
>>>
>>>List FAQ wiki page is located at:
>>> http://si-list.org/wiki/wiki.pl?Si-List_FAQ
>>>
>>>List technical documents are available at:
>>> http://www.si-list.org
>>>
>>>List archives are viewable at:
>>> //www.freelists.org/archives/si-list
>>>or at our remote archives:
>>> http://groups.yahoo.com/group/si-list/messages
>>>Old (prior to June 6, 2001) list archives are viewable at:
>>> http://www.qsl.net/wb6tpu
>>>
>>>
>>>
>>The weirsp@xxxxxxxxxx e-mail address will terminate March 31, 2005.
>>Please update your address book with weirsi@xxxxxxxxxx
>>
>>
>>------------------------------------------------------------------
>>To unsubscribe from si-list:
>>si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
>>
>>or to administer your membership from a web page, go to:
>>//www.freelists.org/webpage/si-list
>>
>>For help:
>>si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
>>
>>List FAQ wiki page is located at:
>> http://si-list.org/wiki/wiki.pl?Si-List_FAQ
>>
>>List technical documents are available at:
>> http://www.si-list.org
>>
>>List archives are viewable at:
>> //www.freelists.org/archives/si-list
>>or at our remote archives:
>> http://groups.yahoo.com/group/si-list/messages
>>Old (prior to June 6, 2001) list archives are viewable at:
>> http://www.qsl.net/wb6tpu
>>
>>
>>
>
>The weirsp@xxxxxxxxxx e-mail address will terminate March 31, 2005.
>Please update your address book with weirsi@xxxxxxxxxx
>
>
>------------------------------------------------------------------
>To unsubscribe from si-list:
>si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
>
>or to administer your membership from a web page, go to:
>//www.freelists.org/webpage/si-list
>
>For help:
>si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
>
>List FAQ wiki page is located at:
> http://si-list.org/wiki/wiki.pl?Si-List_FAQ
>
>List technical documents are available at:
> http://www.si-list.org
>
>List archives are viewable at:
> //www.freelists.org/archives/si-list
>or at our remote archives:
> http://groups.yahoo.com/group/si-list/messages
>Old (prior to June 6, 2001) list archives are viewable at:
> http://www.qsl.net/wb6tpu
>
>
>
>
>
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List FAQ wiki page is located at:
http://si-list.org/wiki/wiki.pl?Si-List_FAQ
List technical documents are available at:
http://www.si-list.org
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
