Mikhail: I believe that more analysis will reveal that a redesign is required. I was involved in a similar situation myself at a company where the engineers had started using Actel FPGA devices without realizing just how fast their edge rates were at 1ns. Since most engineers had not worried about terminating FPGA outputs before, they did not think it would be necessary with Actel devices. In the end however, large amounts of overshoot and undershoot were experienced. Even though the boards were working, it was decided that for reliability purposes it was best to do a redesign with termination resistors at the FPGA outputs. Jeff Krinsky ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu