[SI-LIST] Re: R: Rogers4003 Board Characterization
- From: "Loyer, Jeff" <jeff.loyer@xxxxxxxxx>
- To: <ryan.satrom@xxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Sat, 15 Apr 2006 17:27:19 -0700
I've seen quite a few posts regarding exotic effects that might ruin
your correlation, but I would first look to solve your problem by
looking for some simple "gotchas", especially if you can only correlate
to 5GHz.
1) I wouldn't use microstrip to try to measure Er. There are too many
ways of getting wrong results (assumptions about trace geometries,
including plating; soldermask properties and geometry; etc.). I would
only use stripline, whose propagation speed will depend on Er only, and
be completely independent of trace geometry.
2) I would urge you to try to measure change in propagation time instead
of the absolute value, to determine Er. For instance, on any test board
I do, I always include several lengths of traces. That way I can
measure the propagation delay of those, and know that the delta is due
only to the difference in trace length - the launch effects are
effectively de-embedded. Of course, this is done automatically with TRL
cal. structures, but I would also do it if I was only counting on SOLT.
Measuring prop. delay on a single trace is too error-prone, in my
opinion.
If your board doesn't have these various lengths, I would consider
sacrificing one board and sawing it to measure the prop. delay of
different lengths of stripline traces. Start by sawing the board at the
very end of a trace, and TDR'ing that trace from the other end. Then
cut an inch or two (depending on the length of the trace) and measure
again. Repeat if you can...
3) Your experience with measurement showing more loss than simulations
agrees with mine, but is dependent on the simulator. I've had best
correlation with ADS and XFX (expensive 3D simulators haven't proven
themselves more accuate in this regard, to me), without having to
account for surface roughness. My correlations have been up to 20GHz.
I will say that my experience is anecdotal (taking a few test boards I
had lying around and measuring/modeling/correlating them), and not
comprehensive.
Good luck,
Jeff Loyer
Disclaimer:
The content of this message is my personal opinion only and although I
am an employee of Intel, the statements I make here in no way represent
Intel's position on the issue, nor am I authorized to speak on behalf of
Intel on this matter.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of ryansatrom
Sent: Friday, April 14, 2006 8:08 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: R: Rogers4003 Board Characterization
To All-
Thanks to all who have posted. A little more background on the board
(if interested):
-Trace Thickness: Microstrip=3D3D16mil; Stripline=3D3D8mil (before fab =
-
trace loses about 0.5mil on each side through manufacturing process)
-Board Thickness ~200mil.
-Layer Thickness =3D3D 8mil
-Hard-gold electrolytic plating of 15-50mils thickness
The launch structures, and a small portion of the trace was modeled in
HFSS. I added a 0.3mil layer of soldermask (used FR4 material) to
model.
From all of your responses, it appears the most important parameters
that i have not included in my models are surface roughness and
frequency-dependent dielectric. HFSS can account for both of them. =20
I will put those into the model and see if it helps.
ED - I am not familiar with correlating sick and surface roughness. How
can i correlate these values to the capacitance?
Thank you very much for the replies. Any more thoughts will certainly
be appreciated. If anybody is interested in working with some of the
data, feel free to email me at ryan.satrom@xxxxxxxxxxxx
Thanks again.
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