[SI-LIST] Re: R: Rogers4003 Board Characterization
- From: "ryansatrom" <ryan.satrom@xxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 14 Apr 2006 15:08:03 -0000
To All-
Thanks to all who have posted. A little more background on the
board (if interested):
-Trace Thickness: Microstrip=3D16mil; Stripline=3D8mil (before fab -
trace loses about 0.5mil on each side through manufacturing process)
-Board Thickness ~200mil.
-Layer Thickness =3D 8mil
-Hard-gold electrolytic plating of 15-50mils thickness
The launch structures, and a small portion of the trace was modeled
in HFSS. I added a 0.3mil layer of soldermask (used FR4 material)
to model.
From all of your responses, it appears the most important parameters
that i have not included in my models are surface roughness and
frequency-dependent dielectric. HFSS can account for both of them.
I will put those into the model and see if it helps.
ED - I am not familiar with correlating sick and surface
roughness. How can i correlate these values to the capacitance?
Thank you very much for the replies. Any more thoughts will
certainly be appreciated. If anybody is interested in working with
some of the data, feel free to email me at ryan.satrom@xxxxxxxxxxxx
Thanks again.
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List FAQ wiki page is located at:
http://si-list.org/wiki/wiki.pl?Si-List_FAQ
List technical documents are available at:
http://www.si-list.org
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
