[SI-LIST] Re: Effects of overshoot/undershoot on long-term reliability

  • From: steve weir <weirsi@xxxxxxxxxx>
  • To: Edi.Fraiman@xxxxxxxxxxxxx, <matusov@xxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
  • Date: Wed, 08 Mar 2006 06:35:06 -0800

Edi, of course anything is worth trying out as an idea, but I think 
raising the impedance of the line will trade overshoot for 
ringback.  The real issue is that with these mega fast edges, even 
fairly small structures ring.  We generally need some loss somewhere 
to bring it under control.

Regards,


Steve.
At 05:43 AM 3/8/2006, Edi Fraiman wrote:
>Hi,
>
>I could suggest you maybe another way solve the overshoot/undershoot
>problem.
>Try simulating the SDRAM interface with different traces thickness (I
>think that more narrow traces should dump the overshoot/undershoot).If
>you achieve better overshoot/undershoot results during simulation than
>you will ask from PCB manufacturer only change the traces thickness
>without relayout and adding serial resistors.=20
>
>Best regards,
>Edi Fraiman=20
>
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
>[mailto:si-list-bounce@xxxxxxxxxxxxx]
> > On Behalf Of Mikhail Matusov
> > Sent: Friday, March 03, 2006 5:34 PM
> > To: si-list@xxxxxxxxxxxxx
> > Subject: [SI-LIST] Effects of overshoot/undershoot on long-term
> > reliability
> >=20
> > Dear experts,
> >=20
> > I designed a card based on the ADI TS201 TigerSHARC EZ-KIT evaluation
> > board
> > schematics. The TS201 has 2.5V 3.3V-tolerant I/Os . On this board it
>is
> > directly connected to a 3.3V Micron SDRAM.  Unfortunately, we had not
> > simulated this interface before going into the layout. When we did we
> > found
> > that there is a huge overshoot on SDRAM read reaching almost 5V at the
>DSP
> > pins. Our SI subcontractor recommends adding series terminations at
>the
> > SDRAM pins. At this point it would mean major PCB redesign. I pulled
>an
> > EZ-KIT card and captured the read cycle to verify the simulation
>results
> > and
> > found that the board behaves exactly as in simulation, i.e. the DSP
>chip
> > is
> > constantly subjected to this huge overshoot. However, the board works
>fine.
> > So, I was wondering how I could estimate the risk of leaving the
>design as
> > is?
> >=20
> >=20
> > Thanks,
> > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> > Mikhail Matusov
> > Hardware Design Engineer
> > Square Peg Communications
> > Tel.: +1 (613) 271-0044 ext.231
> > Fax: +1 (613) 271-3007
> > http://www.squarepeg.ca
> >=20
> >=20
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