[SI-LIST] Re: Rogers4003 Board Characterization
- From: "Bill Dempsey" <bdempsey85@xxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Sat, 15 Apr 2006 10:30:56 -0500
Ryan,
Did I read in your post correctly? "Hard Gold Electrolytic plating"
Hard gold requires a thick nickel layer to be deposited on the transmission
line first before gold and then, if you call it out, soldermask.
Immersion gold process does not deposit nickel on the traces since
soldermask is applied first.
You will see quite unexpected results with your microstrip if you did not
account for the ferro-magnetic effect of the nickel. The nickel will be
around 150-180uin thick.
Hope this helps,
Bill
Msg: #3 in digest
Date: Fri, 14 Apr 2006 15:08:03 -0000
From: "ryansatrom" <ryan.satrom@xxxxxxxxxxx>
Subject: [SI-LIST] Re: R: Rogers4003 Board Characterization
To All-
Thanks to all who have posted. A little more background on the
board (if interested):
-Trace Thickness: Microstrip=3D16mil; Stripline=3D8mil (before fab -
trace loses about 0.5mil on each side through manufacturing process)
-Board Thickness ~200mil.
-Layer Thickness =3D 8mil
-Hard-gold electrolytic plating of 15-50mils thickness
The launch structures, and a small portion of the trace was modeled
in HFSS. I added a 0.3mil layer of soldermask (used FR4 material)
to model.
From all of your responses, it appears the most important parameters
that i have not included in my models are surface roughness and
frequency-dependent dielectric. HFSS can account for both of them.
I will put those into the model and see if it helps.
ED - I am not familiar with correlating sick and surface
roughness. How can i correlate these values to the capacitance?
Thank you very much for the replies. Any more thoughts will
certainly be appreciated. If anybody is interested in working with
some of the data, feel free to email me at ryan.satrom@xxxxxxxxxxxx
Thanks again.
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