[SI-LIST] Re: Effects of overshoot/undershoot on long-term reliability
- From: "Grasso, Charles" <Charles.Grasso@xxxxxxxxxxxx>
- To: <Edi.Fraiman@xxxxxxxxxxxxx>, <matusov@xxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 8 Mar 2006 10:27:24 -0700
If your design exceeds the design requirements for the chip then you
cannot guarantee reliability.=20
If you say the problem in simulation - then I suggest you bite the
bullet and relayout your board and add the series Rs.
Best Regards
Charles Grasso
Senior Compliance Engineer
Echostar Communications Corp.
Tel: 303-706-5467
Fax: 303-799-6222
Cell: 303-204-2974
Pager/Short Message: 3032042974@xxxxxxxx
Email: charles.grasso@xxxxxxxxxxxx;
Email Alternate: chasgrasso@xxxxxxxx
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Edi Fraiman
Sent: Wednesday, March 08, 2006 6:44 AM
To: matusov@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Effects of overshoot/undershoot on long-term
reliability
Hi,
I could suggest you maybe another way solve the overshoot/undershoot
problem.
Try simulating the SDRAM interface with different traces thickness (I
think that more narrow traces should dump the overshoot/undershoot).If
you achieve better overshoot/undershoot results during simulation than
you will ask from PCB manufacturer only change the traces thickness
without relayout and adding serial resistors.=3D20
Best regards,
Edi Fraiman=3D20
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Mikhail Matusov
> Sent: Friday, March 03, 2006 5:34 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Effects of overshoot/undershoot on long-term
> reliability
>=3D20
> Dear experts,
>=3D20
> I designed a card based on the ADI TS201 TigerSHARC EZ-KIT evaluation
> board
> schematics. The TS201 has 2.5V 3.3V-tolerant I/Os . On this board it
is
> directly connected to a 3.3V Micron SDRAM. Unfortunately, we had not
> simulated this interface before going into the layout. When we did we
> found
> that there is a huge overshoot on SDRAM read reaching almost 5V at the
DSP
> pins. Our SI subcontractor recommends adding series terminations at
the
> SDRAM pins. At this point it would mean major PCB redesign. I pulled
an
> EZ-KIT card and captured the read cycle to verify the simulation
results
> and
> found that the board behaves exactly as in simulation, i.e. the DSP
chip
> is
> constantly subjected to this huge overshoot. However, the board works
fine.
> So, I was wondering how I could estimate the risk of leaving the
design as
> is?
>=3D20
>=3D20
> Thanks,
> =
=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D=
3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D
> Mikhail Matusov
> Hardware Design Engineer
> Square Peg Communications
> Tel.: +1 (613) 271-0044 ext.231
> Fax: +1 (613) 271-3007
> http://www.squarepeg.ca
>=3D20
>=3D20
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