[SI-LIST] Re: Decoupling capacitor placement
- From: cadpro2k@xxxxxxxxxx
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 17 Aug 2001 08:43:17 -0800
Hi all,
I'm not sure if this is just the 00's version of the good ol' 70's,
"surface mount ain't gonna to work", or the 80's version of "90 degree
bends are bad" or the 90's version of "the 20H rule needs to be adhered
to". Now we have the growing phenom of "two vias per cap/IC pwr pins".
Does ANYONE have data to support this growing virus? I see it all the
more common now days with designs getting faster and faster (or is it
just that new engineers were never taught how to gauge speeds in
college?).
Got a couple problems.
1) Why would you even consider your first scenario unless you've got
loads of board space to utilize? The only time I've really gone to this
technique was on little tester cards. And then I couldn't understand why
an engineer considered this necessary since most of the world goes by
way of opposite side placement. And why does the path need to be from
the plane via thru the cap to the IC pin, since THERE IS plenty of data
available NOT supporting this technique.
2) Two caps per IC pwr pin vs. two vias per cap pwr/gnd pins. What's
with this? I know in theory it makes some sense to those "in the know",
but where is the test data? I can envision this to be the new barrier to
boards that can route with current technologies (mechanical drill) and
those that require new techs (laser drilled/ blind & buried). Say I have
a 680 pin 1mm BGA with 200 pwr/gnd pins (this is more and more common).
How many caps will I need? Does anyone have data to support the
bypassing required for these devices? Certainly not the IC manufacturer
from what I've seen. Now you want me to add two vias per cap pad? Come
on!
Just my $.02 worth. Data verses theory, what do you choose?
Sign me "Frustrated with theory".
Mitch
---------Included Message----------
> Date: Thu, 16 Aug 2001 19:14:27 -0500
> From: <Wei_Chen@xxxxxxxx>
> Reply-To: <Wei_Chen@xxxxxxxx>
> To: <si-list@xxxxxxxxxxxxx>
> Subject: [SI-LIST] Decoupling capacitor placement
>
>
> There are two ways to place a decoupling capacitor for a Vcc
pin:
>
> 1. Place the cap on the top-side of the board and close together
with the
> Vcc pin. Connect Vcc pin to the cap and use two vias from the cap
to the
> power plane and ground plane. This is pin-cap-via topology.
>
> 2. Place the cap on the bottom side of the board (under the IC)
and close to
> the Vcc pin. Connect Vcc to power plane through a via and connect
the cap to
> power and ground plane through 2 vias. This is pin-via/cap-via
topology.
> Basically you used the power plane to connect your Vcc pin and
decoupling
> capacitor.
>
> This is a multi-power/ground plane board.
>
> Which topology would you recommend?
>
> Thanks,
>
> Wei
>
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