[SI-LIST] Re: Decoupling capacitor placement

  • From: "Chung, Chee Yee" <chee.yee.chung@xxxxxxxxx>
  • To: Wei_Chen@xxxxxxxx, si-list@xxxxxxxxxxxxx
  • Date: Fri, 17 Aug 2001 06:42:59 -0700

Wei,
essentially, you are looking at the effective loop inductance from the
capacitor towards the component pins (VCC/VSS).  so, the charge flow is from
the VCC pin, towards the capacitor +ve terminal, and coming out of the -ve
terminal, back towards the VSS pins.  

depending on the plane separation thickness of VCC/VSS (and that they are on
the top few layers rather than bottom few layers) + how close it is to the
pins, config 1 could be better than config 2.  you can do the estimate
either through some equation/hand calculation which will give you first
order estimate, or through modeling (parasitic extraction).

chee-yee

-----Original Message-----
From: Wei_Chen@xxxxxxxx [mailto:Wei_Chen@xxxxxxxx]
Sent: Thursday, August 16, 2001 5:14 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Decoupling capacitor placement



There are two ways to place a decoupling capacitor for a Vcc pin:

1. Place the cap on the top-side of the board and close together with the
Vcc pin. Connect Vcc pin to the cap and use two vias from the cap to the
power plane and ground plane. This is pin-cap-via topology.

2. Place the cap on the bottom side of the board (under the IC) and close to
the Vcc pin. Connect Vcc to power plane through a via and connect the cap to
power and ground plane through 2 vias. This is pin-via/cap-via topology.
Basically you used the power plane to connect your Vcc pin and decoupling
capacitor.

This is a multi-power/ground plane board.

Which topology would you recommend?

Thanks,

Wei 
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