[SI-LIST] Re: Decoupling capacitor placement

  • From: Ray Anderson <Raymond.Anderson@xxxxxxx>
  • To: Christopher.Crowley@xxxxxxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
  • Date: Thu, 29 May 2003 11:51:41 -0700 (PDT)

>
>Hello,
>I am looking to add more decoupling to a high pin count 
>BGA and due to routing constraints I am unable to get as 
>close as I would like to the device.  Does anyone have any 
>experience with making one land pad and then soldering a couple 
>caps on top of each other to the one land area?  Say something like 
>a 0603 .01uf on top of another 0603 .001uf.  I see this as an easy way 
>to get close to the device as well as reduce lead and via inductance.  
>Have I missed something electrically fundamental or are there production level 
>assembly issues with this method?
>
>Thanks,
>Chris
>
>

Chris-

While the "piggy-back" method of mounting may look like a good idea at
first glance, there are a couple of things that you may want to consider
and look out for.

When you mount one cap on top of another you are lengthing the vertical
current path to the second decap. This adds extra mounting inductance.
The extra inductance will do at least two things: 1) reduce the effectiveness
of your added cap., 2) may be the cause of an excessive anti-resonance peak
in the impedance profile as the result of the interaction of the inductance
and the two decaps. (with low ESR caps this can be especially problematic)

As far as mfg concerns go, I'm sure there are some, but not being a 
manufacturing
type I'll just point out the most obvious one that occurs to me: you probably
can't automatically pick and place the second decap, it becomes a manual 
operation.

-Ray Anderson
Sun Microsystems Inc.

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