[SI-LIST] Re: HANDLING HIGH-SPEED BURSTs
- From: Vinu Arumugham <vinu@xxxxxxxxx>
- To: kowal@xxxxxxxx
- Date: Fri, 17 Aug 2001 09:04:04 -0700
How about using serial to parallel converters like MC100EP445 before the FPGA?
Thanks,
Vinu
"Kowal, Keith" wrote:
> Hi,
> Take a look at Altera's FPGA family and their latest
> chips related to clock recovery, LVDS ,etc.
>
> good luck
> keith kowal
> Digital Networks, LLC
>
> -----Original Message-----
> From: Lyke James Civ AFRL/VSSE [mailto:lyke@xxxxxxxxxx]
> Sent: Friday, August 17, 2001 9:32 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] HANDLING HIGH-SPEED BURSTs
>
> In a high-speed data capture application, we are looking at data incoming
> rates as high as 2GSAMPS in a burst. Even though on average the data rates
> are low enough to process in a very high end FPGA (obviously desirable for
> flexibility), the burst rate (up to 65536 samples at a time) is impossibly
> fast. Of course, things like "FIFO" come to mind, but I have been unable to
> locate any component that operates at that rate? Does anyone know of an
> approach that does not involve spinning a custom GaAs ASIC to handle this
> "bursty" problem?
>
> jim
>
> ============================
> Jim Lyke, AFRL/VSEE, 505-846-5812 / fax 853-3393
>
> I was in a job interview and I opened a book and started reading. Then I
> said to
> the guy, "Let me ask you a question. If you are in a spaceship that is
> traveling
> at the speed of light, and you turn on the headlights, does anything
> happen?" He
> said, "I don't know." I said, "I don't want your job." -- Steven Wright
>
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