[SI-LIST] Re: Decoupling capacitor placement
- From: "Salkow, Steven" <steven.salkow@xxxxxxxx>
- To: "'Christopher.Crowley@xxxxxxxxxxxxxxxxx'" <Christopher.Crowley@xxxxxxxxxxxxxxxxx>,si-list@xxxxxxxxxxxxx, si-list-bounce@xxxxxxxxxxxxx
- Date: Thu, 29 May 2003 12:26:50 -0700
To circumvent the inductance of a via, choose a low inductance cap that has
the 0508 aspect ratio over the 0805
see
http://www.johansondielectrics.com/products/lic/JDI_Low-Induct_11-02.pdf
Steven Salkow
Lockheed Martin
3200 Zanker Rd
San Jose, CA 95134
(408) 473-4058
steven.salkow@xxxxxxxx
Fax (408) 473-3044
> -----Original Message-----
> From: Christopher.Crowley@xxxxxxxxxxxxxxxxx
> [SMTP:Christopher.Crowley@xxxxxxxxxxxxxxxxx]
> Sent: Thursday, May 29, 2003 7:25 AM
> To: si-list@xxxxxxxxxxxxx; si-list-bounce@xxxxxxxxxxxxx
> Subject: [SI-LIST] Decoupling capacitor placement
>
> Hello,
> I am looking to add more decoupling to a high pin count BGA and due to
> routing
> constraints I am unable to get as close as I would like to the device.
> Does anyone
> have any experience with making one land pad and then soldering a couple
> caps
> on top of each other to the one land area? Say something like a 0603
> .01uf on top of
> another 0603 .001uf. I see this as an easy way to get close to the device
>
> as well as reduce
> lead and via inductance. Have I missed something electrically fundamental
>
> or are
> there production level assembly issues with this method?
>
> Thanks,
> Chris
>
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