[SI-LIST] Re: DDR3 routing Topology selection

  • From: Sen Velmurugan <sen.velmurugan@xxxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Thu, 20 Jun 2013 11:03:13 -0700

You need to check the setup n hold time margin for the choice of 
topology before finalizing.

Msg: #12 in digest
From: "Vinod Kumar"<vinod.kumar@xxxxxxxxxxxx>
Subject: [SI-LIST] Re: DDR3 routing Topology selection
Date: Wed, 19 Jun 2013 17:09:45 +0530

Hi Hermann,

Thank you very much for your inputs.

And extra time for calibration is not an issue. My main concern is the
support for DDR3 calibration with the BSP that I got from vendor.
In the reference board, there are four DDR3 chips and T-topology is used and
there are no terminations. So I am not sure if write leveling is supported
in the reference code. I was actually thinking about those additional
efforts if there is no code support. BTW, I am inclined more towards fly by


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