[SI-LIST] Re: DDR3 routing Topology selection

  • From: "Vinod Kumar" <vinod.kumar@xxxxxxxxxxxx>
  • To: "'Hermann Ruckerbauer'" <Hermann.Ruckerbauer@xxxxxxxxxxxxx>
  • Date: Wed, 19 Jun 2013 17:09:45 +0530

Hi Hermann, 

Thank you very much for your inputs.

And extra time for calibration is not an issue. My main concern is the
support for DDR3 calibration with the BSP that I got from vendor. 
In the reference board, there are four DDR3 chips and T-topology is used and
there are no terminations. So I am not sure if write leveling is supported
in the reference code. I was actually thinking about those additional
efforts if there is no code support. BTW, I am inclined more towards fly by
topology.

Regards,
Vinod


-----Original Message-----
From: Hermann Ruckerbauer [mailto:Hermann.Ruckerbauer@xxxxxxxxxxxxx] 
Sent: Wednesday, June 19, 2013 4:41 PM
To: Vinod Kumar
Cc: doltbird1972@xxxxxxxxxxx; sonu.goyal@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: DDR3 routing Topology selection

Hello Vinod,

my comment was not that I would be concerned regarding this overshoots, it
was just that it looks different than what was mentioned in the text.
Solving this via Drive strength setting is the right way to do.

Regarding the Write leveling:
Does it hurt you when the calibration are executed? it might take some short
time at powerup, but if you are not critical on this one I would leave it
in.
Otherwise you have to do quite some measurements to figure out the best
settings e. g. for PVT variations (not really T, and maybe not V, but
Process is considered by the calibration routines).
I had concerns in the beginning when these routines have been introduced,
but in the meantime they are really robust.
So if there is nor specific reason (like Power up time) I would utilize this
feature in any hardware ..

Hermann

Am 19.06.2013 12:03, schrieb Vinod Kumar:
> Hi Hermann,
>
> The overshoot/undershoot problem for T-routing is solved by changing 
> the drive impedance on controller side.
> I am working along with Sonu on this and the data given by Sonu was 
> for 34 Ohm driving impedance. For 40Ohm driving impedance, the voltage 
> swing is well within 0V to 1.5V.
>
> Now question is whether the efforts required for DDR3 
> calibration/write leveling for Fly By topology are worth its SI value 
> for a two chip DDR3 solution. We are still pondering on it.
>
> Regards,
> Vinod
>
> -----Original Message-----
> From: Hermann Ruckerbauer [mailto:Hermann.Ruckerbauer@xxxxxxxxxxxxx]
> Sent: Wednesday, June 19, 2013 3:03 PM
> To: doltbird1972@xxxxxxxxxxx
> Cc: sonu.goyal@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx; 'Vinod Kumar'
> Subject: Re: [SI-LIST] Re: DDR3 routing Topology selection
>
> Hello,
>
> for two devices at 533 you might have a chance to work without CA 
> Termination for the T-Branch.
> For Flyby this might not be possible.
>
> Regarding your comments it looks T is having higher overshoots and 
> therefore I would excpect FlyBy to show better SI (what is different 
> than what you write).
> T seems to have overshoots, while the levels for FlyBy seems nicly 
> terminated and therefore not even reaching the full swing voltage rails ..
>
> Best regards
>
> Hermann
>
> EKH - EyeKnowHow
> Hermann Ruckerbauer
> www.EyeKnowHow.de
> Hermann.Ruckerbauer@xxxxxxxxxxxxx
> Itzlinger Strasse 21a
> 94469 Deggendorf
> Tel.: +49 (0)991 / 29 69 29 05
> Mobile:       +49 (0)176  / 787 787 77
> Fax:  +49 (0)3212 / 121 9008
>
> schrieb Doltbird1972:
>> Sonu,
>> As for 2 DDR3 chips on your board, it does not matter what kind of 
>> topology you are using. Just thinking about convenience for your layout.
>> ( The thing will be totally different when more than 4 chips. )
>>
>> Regards!
>>
>> ShaoPeng
>> IEEE Member, Senior SI Consultant and PCB Engineer
>>
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx
>> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Sonu Goyal
>> Sent: 2013年6月19日 16:34
>> To: si-list@xxxxxxxxxxxxx
>> Cc: Vinod Kumar
>> Subject: [SI-LIST] DDR3 routing Topology selection
>>
>> Hi
>> We are designing a custom board where 2 DDR3 chips (533MHz) are 
>> interfaced with processor. There are two routing toplogies which we 
>> are considering for our layout.
>> 1. T topology
>> 2. Fly-By topology
>>
>> We have done pre-layout SI simulation using hyperlynx. As we know  
>> for
>> DDR3 flyby topology is recommended by JEDEC but according to our 
>> simulation results  T topology is looking better.
>>
>> In T topology overshoot is coming 1.6V and undershoot is -0.1V and in 
>> Fly-By topology overshoot is coming at 1.225V and undershoot at 240mV.
>> I am attaching snapshots here. Please confirm what topology flyby or 
>> T topology we should prefer for our board.
>>
>> Regards
>> Sonu Goyal
>>
>>
>>
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-- 

EKH - EyeKnowHow
Hermann Ruckerbauer
www.EyeKnowHow.de
Hermann.Ruckerbauer@xxxxxxxxxxxxx
Itzlinger Strasse 21a
94469 Deggendorf
Tel.:   +49 (0)991 / 29 69 29 05
Mobile: +49 (0)176  / 787 787 77
Fax:    +49 (0)3212 / 121 9008

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