[SI-LIST] DDR3 routing Topology selection

  • From: Sonu Goyal <sonu.goyal@xxxxxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Wed, 19 Jun 2013 14:04:12 +0530

We are designing a custom board where 2 DDR3 chips (533MHz) are interfaced
with processor. There are two routing toplogies which we are considering
for our layout.
1. T topology
2. Fly-By topology

We have done pre-layout SI simulation using hyperlynx. As we know  for DDR3
flyby topology is recommended by JEDEC but according to our simulation
results  T topology is looking better.

In T topology overshoot is coming 1.6V and undershoot is -0.1V and in
Fly-By topology overshoot is coming at 1.225V and undershoot at 240mV. I am
attaching snapshots here. Please confirm what topology flyby or T topology
we should prefer for our board.

Sonu Goyal

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