[SI-LIST] Re: DDR3 routing Topology selection
- From: Doltbird1972 <doltbird1972@xxxxxxxxxxx>
- To: <vinod.kumar@xxxxxxxxxxxx>, "'Hermann Ruckerbauer'" <Hermann.Ruckerbauer@xxxxxxxxxxxxx>
- Date: Wed, 19 Jun 2013 19:31:17 +0800
Whether you need to calibrate the write leveling depends how much the timing
delay mismatch among your Address signals.
1. If the timing mismatch is within your controller's specification, then
just forget it;
2. if it is out of the specification, you may choose a) do write leveling b)
compensate the delay by tuning the timing delay in Data signals(tricky).
Regards!
ShaoPeng
IEEE Member, Senior SI Consultant and PCB Engineer
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Vinod Kumar
Sent: 2013年6月19日 18:04
To: 'Hermann Ruckerbauer'; doltbird1972@xxxxxxxxxxx
Cc: sonu.goyal@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: DDR3 routing Topology selection
Hi Hermann,
The overshoot/undershoot problem for T-routing is solved by changing the
drive impedance on controller side.
I am working along with Sonu on this and the data given by Sonu was for 34
Ohm driving impedance. For 40Ohm driving impedance, the voltage swing is
well within 0V to 1.5V.
Now question is whether the efforts required for DDR3 calibration/write
leveling for Fly By topology are worth its SI value for a two chip DDR3
solution. We are still pondering on it.
Regards,
Vinod
-----Original Message-----
From: Hermann Ruckerbauer [mailto:Hermann.Ruckerbauer@xxxxxxxxxxxxx]
Sent: Wednesday, June 19, 2013 3:03 PM
To: doltbird1972@xxxxxxxxxxx
Cc: sonu.goyal@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx; 'Vinod Kumar'
Subject: Re: [SI-LIST] Re: DDR3 routing Topology selection
Hello,
for two devices at 533 you might have a chance to work without CA
Termination for the T-Branch.
For Flyby this might not be possible.
Regarding your comments it looks T is having higher overshoots and therefore
I would excpect FlyBy to show better SI (what is different than what you
write).
T seems to have overshoots, while the levels for FlyBy seems nicly
terminated and therefore not even reaching the full swing voltage rails ..
Best regards
Hermann
EKH - EyeKnowHow
Hermann Ruckerbauer
www.EyeKnowHow.de
Hermann.Ruckerbauer@xxxxxxxxxxxxx
Itzlinger Strasse 21a
94469 Deggendorf
Tel.: +49 (0)991 / 29 69 29 05
Mobile: +49 (0)176 / 787 787 77
Fax: +49 (0)3212 / 121 9008
schrieb Doltbird1972:
> Sonu，
> As for 2 DDR3 chips on your board, it does not matter what kind of
> topology you are using. Just thinking about convenience for your layout.
> ( The thing will be totally different when more than 4 chips. )
>
> Regards!
>
> ShaoPeng
> IEEE Member, Senior SI Consultant and PCB Engineer
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Sonu Goyal
> Sent: 2013年6月19日 16:34
> To: si-list@xxxxxxxxxxxxx
> Cc: Vinod Kumar
> Subject: [SI-LIST] DDR3 routing Topology selection
>
> Hi
> We are designing a custom board where 2 DDR3 chips (533MHz) are
> interfaced with processor. There are two routing toplogies which we
> are considering for our layout.
> 1. T topology
> 2. Fly-By topology
>
> We have done pre-layout SI simulation using hyperlynx. As we know for
> DDR3 flyby topology is recommended by JEDEC but according to our
> simulation results T topology is looking better.
>
> In T topology overshoot is coming 1.6V and undershoot is -0.1V and in
> Fly-By topology overshoot is coming at 1.225V and undershoot at 240mV.
> I am attaching snapshots here. Please confirm what topology flyby or T
> topology we should prefer for our board.
>
> Regards
> Sonu Goyal
>
>
>
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