[SI-LIST] asymmetrical stack-ups

  • From: train stop <trainstopp@xxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Thu, 20 Jun 2013 13:10:00 -0500

What are the general guidelines regarding implementing asymetrical
stack-ups to compensate for a GND-Sig-Sig-PWR in order to encourage
coupling to the utility layers for return current paths?  Are there
recommendations to the thickness of the dielectric thickness between the
Sig-Sig layer versus the GND-SIG or SIG-PWR.....so for interfaces below
400Mhz would an acceptable guideline be x3's.......I am just looking for
some guidelines given lack of access to modeling tools.

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