[SI-LIST] Re: Xilinx decoupling
- From: "Martin Euredjian" <martin@xxxxxxxxxxxxxx>
- To: "Georg Ramsch" <Georg.Ramsch@xxxxxxxxxxx>,<si-list@xxxxxxxxxxxxx>
- Date: Mon, 16 Dec 2002 15:50:31 -0800
Thanks for the note.
My approach has been to start with the Xilinx "standard routing" document
(UG002, v1.2, page 475) and manually create connections to relevant logic
outside the chip.
With this in place I crated the schematic symbols and assigned signals to
match the standard routing. Hopefully this means that the schematics will
require little, if any modifications due to routing issues, since every
single signal's route to its destination has already been studied and placed
by hand.
I had some concerns about assigning wide busses across bank boundaries and
asked a couple of questions about this on this list. Other than that, this
is the only way I can put sweat equity into a process that has the potential
to be very expensive and painful if one does not do this sort of thing.
Clearly there has to be a better way to do this. I'm not sure how the $100K
tools do it, I'm just using PCAD ... enough said. The real layout will be
done by a vendor with more advanced tools.
I have a better sense of proportion when it comes to the layout of the >80
capacitors required by this device now. We'll see how it turns out.
Thanks,
===============================
Martin Euredjian
eCinema Systems, Inc.
voice: 661-305-9320
fax: 661-775-4876
martin@xxxxxxxxxxxxxx
www.ecinemasys.com
===============================
-----Original Message-----
From: Georg Ramsch [mailto:Georg.Ramsch@xxxxxxxxxxx]
Sent: Monday, December 16, 2002 2:59 PM
To: martin@xxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: Xilinx decoupling
Hello, Martin !
I am just doing the layout for a FG456 package; it is very time consuming
and
one should not use all pins ( my pcb is 6 layers of copper, 2 are power,
rest 4
layers for signals ).
Some ideas:
a) routing the two outer rows / columns on the 1st layer, reach A3 - A5 /
E1 -
E5 etc. with the 2 further signal layers.
The NCs give some advantage.
Sometimes it is annoying to to change the schematic every 20 min for
better
routing, but may be worth it.
b) do not connect every power pin to the power plane, but may be 4 Gnd to 1
via
for example( total 9 Gnd vias at the center );
such reducing the swiss cheese effect.
If a Gnd planes is just at layer 2, the effect of increased Lvia should
not
be so strong.
==> Comments are welcome!
c) Having a look at the resonant frequencies of ceramic capacitors shows a
range
of the resonant frequencies
between 10 MHz - 50 MHz mostly for 33 - 100nF types.
Blocking higher frequencies is possible with embedded capacitance ( 2 -
4
mil spacing between power planes ).
The location of the caps is perhaps not so critical, if such an embedded
capacitance exists.
==> Can anybody give information about the dependancy of plane impedance
and
the blocking effect of a cap?
CU
Georg
Martin Euredjian wrote:
> Mark,
>
> > What is it about a 1mm pitch device that prevents you from
> > putting enough capacitors on the board?
>
> Where I see a problem is in the inner corner of a package. I'm not doing
> the final layout myself, however, I am trying to specify an attainable
> number of caps in the schematic. I'm doing a rough layout in order to get
> at such things as pin assignments (fanout dependant) and the number and
type
> of decoupling caps for some of these large pin count devices.
>
> I'm probably missing something very fundamental, so I'd appreciate any and
> all input on this matter. I'm looking at the FG456 package. Each of the
> inner corners have 4x VCCAUX balls and 4x VCCO balls. Outside these
> corners, you can cover most of the VCCO with 0402's between the VCCO via
and
> the corresponding GND via. However, once you get to the inner corners,
you
> run out of space. How do you place 8 caps where you can barely fit one.
Of
> course, I'm going on the assumption (rule?) that you don't want your HF
caps
> centimeters away from these pins, but as close as possible ~ 1-2mm trace
> max.
>
> I've attached a JPEG image depicting the above. It won't make it onto the
> list but it should arrive at your off-list email address.
>
> Thanks,
>
> ===============================
> Martin Euredjian
> eCinema Systems, Inc.
> voice: 661-305-9320
> fax: 661-775-4876
> martin@xxxxxxxxxxxxxx
> www.ecinemasys.com
> ===============================
>
> -- Binary/unsupported file stripped by Ecartis --
> -- Type: image/jpeg
> -- File: Decoupling copy.jpg
>
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