Posts for si-list, 12-2002

Browse: Last Month: 11-2002 Main Archive Page Next Month: 01-2003

» [SI-LIST] Re: hspice simulation issue in VCO -
» [SI-LIST] hspice simulation issue in VCO -
» [SI-LIST] Looking for a paper about spiral inductor. -
» [SI-LIST] Repeat mail - attachment is given below the mail -
» [SI-LIST] Repeat mail with Attachment -
» [SI-LIST] Job Hunting -
» [SI-LIST] Monte Carlo -
» [SI-LIST] Re: Max Trace current -
» [SI-LIST] Re: Max Trace current -
» [SI-LIST] Max Trace current -
» [SI-LIST] Help for PCB stackup! -
» [SI-LIST] Help for PCB stackup! -
» [SI-LIST] Re: Ethernet MUX -
» [SI-LIST] Re: Ethernet MUX -
» [SI-LIST] IEEE co-sponsored EMI/EMC seminar in India -
» [SI-LIST] Re: Trace Length Calculation -
» [SI-LIST] Trace Length Calculation -
» [SI-LIST] CALL FOR EMC COMPUTER MODELING AND SIMULATION DEMONSTRATIONS -
» [SI-LIST] SPECCTRAQuest users -
» [SI-LIST] Re: simulation -
» [SI-LIST] simulation -
» [SI-LIST] Ethernet MUX -
» [SI-LIST] Re: Question: Energy X'mit Directions of Maxwell's eq.s -
» [SI-LIST] Re: Processor Data bus topology -
» [SI-LIST] Re: Processor Data bus topology -
» [SI-LIST] Processor Data bus topology -
» [SI-LIST] Re: AWE and NILT -
» [SI-LIST] Re: Differential probe model! -
» [SI-LIST] Re: Differential probe model! -
» [SI-LIST] Differential probe model! -
» [SI-LIST] ESD Protection -
» [SI-LIST] Question: Energy X'mit Directions of Maxwell's eq.s -
» [SI-LIST] Root Pwd -
» [SI-LIST] SPICE simulation -
» [SI-LIST] Re: Better choice for AC Coulplilng(calrification) -
» [SI-LIST] cross-talk between differential lines -
» [SI-LIST] RDRAM -
» [SI-LIST] Re: Question regarding the differential impedance -
» [SI-LIST] Re: Differential Impedance Mismatch Rule of Thumb -
» [SI-LIST] Re: compare ADS dispersion with H-Spice W-element. -
» [SI-LIST] Re: Better choice for AC Coulplilng(calrification) -
» [SI-LIST] Re: Better choice for AC Coulplilng(calrification) -
» [SI-LIST] Better choice for AC Coulplilng(calrification) -
» [SI-LIST] Re: Hspice Limitations -
» [SI-LIST] Re: Question regarding the differential impedance -
» [SI-LIST] Question regarding the differential impedance -
» [SI-LIST] Re: Differential Impedance Mismatch Rule of Thumb -
» [SI-LIST] Re: Hspice Limitations -
» [SI-LIST] Differential Impedance Mismatch Rule of Thumb -
» [SI-LIST] Re: Formula for trace resistance not impedence -
» [SI-LIST] Re: Formula for trace resistance not impedence -
» [SI-LIST] IBIS in HSPICE Question -
» [SI-LIST] Re: Hspice Limitations -
» [SI-LIST] HSpice Question -
» [SI-LIST] Re: Hspice Limitations -
» [SI-LIST] Re: How to connect vias to power ground plane? -
» [SI-LIST] Re: question about connectors and PCB manufacturers -
» [SI-LIST] Re: Formula for trace resistance not impedence -
» [SI-LIST] question about connectors and PCB manufacturers -
» [SI-LIST] Re: Hspice simulation in relates with capacitor -
» [SI-LIST] question about cpb manufacturer's capability -
» [SI-LIST] Formula for trace resistance not impedence -
» [SI-LIST] MICTOR Model -
» [SI-LIST] Re: Current density of Ribbon Cable -
» [SI-LIST] Re: Hspice Limitations -
» [SI-LIST] Re: Better choice for AC coupling -
» [SI-LIST] Better choice for AC coupling -
» [SI-LIST] Current density of Ribbon Cable -
» [SI-LIST] Hspice Limitations -
» [SI-LIST] Re: Hspice simulation in relates with capacitor -
» [SI-LIST] Hspice simulation in relates with capacitor -
» [SI-LIST] How to connect vias to power ground plane? -
» [SI-LIST] Re: DIMM Power Consumption -
» [SI-LIST] ADC Grounding question - FULLY differential system -
» [SI-LIST] Re: DIMM Power Consumption -
» [SI-LIST] DIMM Power Consumption -
» [SI-LIST] IBIS model for switch -
» [SI-LIST] Via Placement between two Differential-Pair Signals -
» [SI-LIST] Repost: Accelerant Networks, Dr. Howard Johnson 6-12.5Gb/s backplane design seminar January 31,2003 -
» [SI-LIST] compare ADS dispersion with H-Spice W-element. -
» [SI-LIST] Regarding lost messages....... -
» [SI-LIST] Re: Xilinx decoupling -
» [SI-LIST] Re: Xilinx decoupling -
» [SI-LIST] Re: Xilinx decoupling -
» [SI-LIST] Re: TMS320 DSP -
» [SI-LIST] Re: TMS320 DSP -
» [SI-LIST] Re: TMS320 DSP -
» [SI-LIST] TMS320 DSP -
» [SI-LIST] Re: Xilinx decoupling -
» [SI-LIST] Re: Xilinx decoupling -
» [SI-LIST] Re: Differential Impedance; Traces w/o Ref Plane -
» [SI-LIST] Re: Xilinx decoupling -
» [SI-LIST] Re: Dispersion -
» [SI-LIST] Re: FW: Backplane Edge Plating -
» [SI-LIST] Re: Differential Impedance; Traces w/o Ref Plane -
» [SI-LIST] Re: Xilinx decoupling -
» [SI-LIST] Employment Opportunity in Bay Area -
» [SI-LIST] Re: Xilinx decoupling -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: Xilinx decoupling -
» [SI-LIST] Re: Xilinx decoupling -
» [SI-LIST] Re: Xilinx decoupling -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: Dispersion -
» [SI-LIST] Analogue & Digital Ground -
» [SI-LIST] Re: Dispersion -
» [SI-LIST] Re: Xilinx decoupling -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Xilinx decoupling -
» [SI-LIST] Re: FW: Backplane Edge Plating -
» [SI-LIST] Re: FW: Backplane Edge Plating -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: Dispersion -
» [SI-LIST] Re: IBIS model -
» [SI-LIST] HSTL classes and SSTL2 -
» [SI-LIST] Buffers -
» [SI-LIST] IBIS model -
» [SI-LIST] Re: differential recevier parameters -
» [SI-LIST] differential recevier parameters -
» [SI-LIST] Job opportunity -
» [SI-LIST] Re: Dispersion -
» [SI-LIST] Re: Dispersion -
» [SI-LIST] Re: Yet another HSPICE error message -
» [SI-LIST] Re: Dispersion -
» [SI-LIST] HSTL classes and SSTL2 -
» [SI-LIST] FW: Re: Ground, the preferred reference plane -
» [SI-LIST] Re: Dispersion -
» [SI-LIST] Re: Dispersion -
» [SI-LIST] Re: Dispersion -
» [SI-LIST] AW: Yet another HSPICE error message -
» [SI-LIST] spice -
» [SI-LIST] Which is Better Topology. -
» [SI-LIST] Re: Ground, the preferred reference plane -
» [SI-LIST] Re: Ground, the preferred reference plane -
» [SI-LIST] Hot Signal Integrity Position-Bay Area -
» [SI-LIST] Steve Wood/TOSHIBA_TEE is out of the office. -
» [SI-LIST] Re: Ground, the preferred reference plane -
» [SI-LIST] Re: Ground, the preferred reference plane -
» [SI-LIST] Re: Ground, the preferred reference plane -
» [SI-LIST] Re: Ground, the preferred reference plane -
» [SI-LIST] Re: Ground, the preferred reference plane -
» [SI-LIST] Question about "Multi-terminal networks" element in H-SPICE -
» [SI-LIST] Re: Return paths -
» [SI-LIST] Re: Dispersion -
» [SI-LIST] Re: Often overlooked effect of ground breaks -
» [SI-LIST] Paralleling Connector Pins -
» [SI-LIST] Return paths -
» [SI-LIST] Re: Ground, the preferred reference plane -
» [SI-LIST] Re: Dispersion -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: Ground, the preferred reference plane -
» [SI-LIST] Hardware Job Interview Questions ! -
» [SI-LIST] Re: Ground, the preferred reference plane -
» [SI-LIST] Re: Ground, the preferred reference plane -
» [SI-LIST] Re: Ground, the preferred reference plane -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: Ground, the preferred reference plane -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: Ground, the preferred reference plane -
» [SI-LIST] Re: Ground, the preferred reference plane -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: Ground, the preferred reference plane -
» [SI-LIST] Re: Ground, the preferred reference plane -
» [SI-LIST] Re: Ground, the preferred reference plane -
» [SI-LIST] Re: Often overlooked effect of ground breaks -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: Ground, the preferred reference plane -
» [SI-LIST] [SI-LIST]How to do the inductor layout in cadence? -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: IPC-D-275 -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: Ground, the preferred reference plane -
» [SI-LIST] Re: Extra symbols -
» [SI-LIST] Extra symbols -
» [SI-LIST] Re: Ground, the preferred reference plane -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: Ground, the preferred reference plane -
» [SI-LIST] Re: Dispersion -
» [SI-LIST] IPC-D-275 -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: USB2.0 simulation by XTK! -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: Dispersion -
» [SI-LIST] Re: Ground, the preferred reference plane -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: Dispersion -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: Differential Impedance; Traces w/o Ref Plane -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: Dispersion -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: Ground, the preferred reference plane -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] USB2.0 simulation by XTK! -
» [SI-LIST] Re: CosmoScope automatic scripts -
» [SI-LIST] Re: CosmoScope automatic scripts -
» [SI-LIST] mixed s-parameter and spice simulation -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: The crosstalk of transmission line when itiscompletelymatched -
» [SI-LIST] Re: Hspice TR# files -
» [SI-LIST] Package Stack-up -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: Hspice TR# files -
» [SI-LIST] Re: Unforeseen resonance -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: Unforeseen resonance -
» [SI-LIST] Re: DDR delay & skew -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: clock skew -
» [SI-LIST] Unforeseen resonance -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: DDR delay & skew -
» [SI-LIST] clock skew -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: Hspice TR# files -
» [SI-LIST] Inductance and ITRS roadmap -
» [SI-LIST] Re: The crosstalk of transmission line when it iscompletelymatched -
» [SI-LIST] DDR delay & skew -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: Hspice TR# files -
» [SI-LIST] Re: Hspice TR# files -
» [SI-LIST] Hspice TR# files -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: The crosstalk of transmission line when it is completelymatched -
» [SI-LIST] Meeting Notice, Tue, 10/Dec/02, An Overview of Recent Developments in Nanotechnology -
» [SI-LIST] Re: The crosstalk of transmission line when it is completelymatched -
» [SI-LIST] Re: CosmoScope automatic scripts -
» [SI-LIST] FW: FW: RS422/485 -
» [SI-LIST] Re: Power/Ground Bounce !!! -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] CosmoScope automatic scripts -
» [SI-LIST] DSP by-pass capacitor -
» [SI-LIST] Power/Ground Bounce !!! -
» [SI-LIST] E-spice -
» [SI-LIST] Often overlooked effect of ground breaks -
» [SI-LIST] Re: The crosstalk of transmission line when it iscompletelymatched -
» [SI-LIST] Re: basic doubt in board design -
» [SI-LIST] Re: basic doubt in board design -
» [SI-LIST] Re: basic doubt in board design -
» [SI-LIST] Re: S-parameter to SPICE -
» [SI-LIST] basic doubt in board design -
» [SI-LIST] Re: S-parameter to SPICE -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] RE SI Job posting - Vancouver Canada -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] HELP -
» [SI-LIST] substrate can be used more than 40 GHz -
» [SI-LIST] Re: (no subject) -
» [SI-LIST] Re: (no subject) -
» (no subject) -
» [SI-LIST] Re: substrate can be used more than 40 GHz -
» [SI-LIST] Re: How to measure the resistance between handle and panel -
» [SI-LIST] Re: Waveform Measurements -
» [SI-LIST] Re: testing SDRAM by Boundary Scan -
» [SI-LIST] Re: The crosstalk of transmission line when it is completelymatched -
» [SI-LIST] The crosstalk of transmission line when it is completely matched -
» [SI-LIST] How to measure the resistance between handle and panel -
» [SI-LIST] Job Opening at Altera -
» [SI-LIST] Re: Reference voltages in IBIS model -
» [SI-LIST] Re: Reference voltages in IBIS model -
» [SI-LIST] LVDS 100 ohm differential -
» [SI-LIST] Re: crosstalk -
» [SI-LIST] Reference voltages in IBIS model -
» [SI-LIST] Re: crosstalk -
» [SI-LIST] Re: Waveform Measurements -
» [SI-LIST] compact-PCI power distribution -
» [SI-LIST] crosstalk -
» [SI-LIST] Re: Star-Hspice working directory -
» [SI-LIST] Job Opening -
» [SI-LIST] Re: Star-Hspice working directory -
» [SI-LIST] Re: Op-amp gain measurement -
» [SI-LIST] Re: Waveform Measurements -
» [SI-LIST] Re: Star-Hspice working directory -
» [SI-LIST] Op-amp gain measurement -
» [SI-LIST] Re: Backplane hole backdrilling -
» [SI-LIST] Re: Waveform Measurements -
» [SI-LIST] Re: power on RAMP -
» [SI-LIST] Re: Waveform Measurements -
» [SI-LIST] Re: Waveform Measurements -
» [SI-LIST] Waveform Measurements -
» [SI-LIST] Re: Waveform Measurements -
» [SI-LIST] Re: Waveform Measurements -
» [SI-LIST] FW: RS422/485 -
» [SI-LIST] Re: Waveform Measurements -
» [SI-LIST] Waveform Measurements -
» [SI-LIST] Re: power on RAMP -
» [SI-LIST] Re: Stripline Characteristic Impedance -
» [SI-LIST] Re: power on RAMP -
» [SI-LIST] power on RAMP -
» [SI-LIST] Re: Stripline Characteristic Impedance -
» [SI-LIST] Re: MPC860 -
» [SI-LIST] MPC860 -
» [SI-LIST] Digital simulation -
» [SI-LIST] DP-SDRAM interface -
» [SI-LIST] Presentation available for download -
» [SI-LIST] Re: simulate ibis model in hspice ??? -
» [SI-LIST] Re: Error in HSPICE -
» [SI-LIST] Re: 10 Layer Board Stack up -
» [SI-LIST] Re: si-list Digest V2 #333 -
» [SI-LIST] Re: 2D, 2.5D,3D -
» [SI-LIST] Re: simulate ibis model in hspice ??? -
» [SI-LIST] Relative permittivity & Loss tangent -
» [SI-LIST] Re: simulate ibis model in hspice ??? -
» [SI-LIST] Re: FPGA supply surrent -
» [SI-LIST] Re: 2D, 2.5D,3D -
» [SI-LIST] Re: 2D, 2.5D,3D -
» [SI-LIST] Re: Question: Reverse current layers? in the skin effect -
» [SI-LIST] simulate ibis model in hspice ??? -
» [SI-LIST] Question: Reverse current layers? in the skin effect -
» [SI-LIST] Re: 10 Layer Board Stack up -
» [SI-LIST] Re: FPGA supply surrent -
» [SI-LIST] Re: 10 Layer Board Stack up -
» [SI-LIST] Re: Decoupling of Oscillator -
» [SI-LIST] Re: 2D, 2.5D,3D -
» [SI-LIST] Re: 10 Layer Board Stack up -
» [SI-LIST] Re: SpecctraQuest Convergence Issue -
» [SI-LIST] Re: FPGA supply surrent -
» [SI-LIST] SpecctraQuest Convergence Issue -
» [SI-LIST] Re: 2D, 2.5D,3D -
» [SI-LIST] Re: programmable clock generator -
» [SI-LIST] Re: programmable clock generator -
» [SI-LIST] 20H Rule revisited -
» [SI-LIST] Re: Decoupling of Oscillator -
» [SI-LIST] Recall: 2D, 2.5D,3D -
» [SI-LIST] Re: 2D, 2.5D,3D -
» [SI-LIST] Re: 2D, 2.5D,3D -
» [SI-LIST] Re: 2D, 2.5D,3D -
» [SI-LIST] Re: 2D, 2.5D,3D -
» [SI-LIST] Re: 2D, 2.5D,3D -
» [SI-LIST] programmable clock generator -
» [SI-LIST] Re: 2D, 2.5D,3D -
» [SI-LIST] Re: 2D, 2.5D,3D -
» [SI-LIST] 2D, 2.5D,3D -
» [SI-LIST] Re: How to select the pullup/pulldwon resistor -
» [SI-LIST] dc2dc -
» [SI-LIST] Re: 10 Layer Board Stack up -
» [SI-LIST] Re: 10 Layer Board Stack up -
» [SI-LIST] Re: 10 Layer Board Stack up -
» [SI-LIST] Re: 10 Layer Board Stack up -
» [SI-LIST] Re: 10 Layer Board Stack up -
» [SI-LIST] Re: 10 Layer Board Stack up -
» [SI-LIST] quartus tool -
» [SI-LIST] FPGA supply surrent -
» [SI-LIST] Re: cross-talk and 20-H -
» [SI-LIST] Re: How to select the pullup/pulldwon resistor -
» [SI-LIST] Re: Stripline Characteristic Impedance -
» [SI-LIST] RS422/485 -
» [SI-LIST] corss-talk and 20-H -
» [SI-LIST] cross talk -
» [SI-LIST] Stripline Characteristic Impedance -
» [SI-LIST] Re: terminator resistor -
» [SI-LIST] terminator resistor -
» [SI-LIST] Re: Power supply noise -
» [SI-LIST] Re: Power supply noise -