[SI-LIST] Re: Xilinx decoupling

Hi Martin and Goerge,
        I would like to make a few points on this very contraversial subject.

Ripple and Jitter:
Mostly ASIC vendors give no specification on the allowable ripple on the power
supply in various frequency bands to allow the designer to anticipate the
ammount of capacitance required.
Some of the ripple will be from an external source i.e DC-DC converters and
other ASICS.
Some will be self generated [mostly high frequencies assiciated with the clocks.
For the low frequencies of a converter a series inductor and single electrolytic
capacitor is required and can be calculated from the relevant specs of converter
and requirement of ASIC device (if known).
An estimate for the distributed high frequency capacitance of the self generated
ripple can be gained gained from the current and the internal rise/fall times of
the gates.
With CMOS technology, the switching action causes the FETS to instantaneously
short the power supply [i.e. during the rise time and fall time]. With the
latest technologies this can be in the order of 100ps.
This creates large ripple on the asic power bus and requires a large number of
ground and power pins to reduce the inductance to the board power planes and
decoupling capacitors.

Q= I*t =C * Vripple-peak 
Here again the vendors give no indication of the ripple requirement or of the
inductance of bus to ball/pin.
What is sure is that the ripple on the internal power bus will be > than on the
external power planes.
From previous emails we should be aware that each gate converts power ripple to
jitter through a function named AM/PM conversion which depends on ampltude and
risetime.
Each application will differ in its jitter requirements [inc. setup and hold
issues]

Regarding Distribution and via inductance.
The fact that the vendor invest much cost in providing many power and ground
pins distributed across the chip gives an indication on the need to keep the
board inductance to a minimum.
Rule of thumb for layout
1.      where possible place a ground plane on the external layer [top/bottom] 
within
the footprint and directly connect as many as possible of the associated ground
pins/balls.
soldermask can be used to prevent leaching [accepted by many board
manufactures].
        This sub-plane should be connected to main ground plane with low 
inductance
vias.
        The reason for the ground and not power is that the power plane will 
have more
ripple that can capacitively couple to the internal ASIC circuitary.

2.      Power and other ground pins/balls should be connected one to one with 
vias
direct to the main power planes. I would agree in minimal trace length and
maximal trace width between via and pad.
        Please minimalise the "sharing of vias". The "swiss cheese effect" does 
not in
any way detriorate the performance of the power planes. I know it increases cost
but we have to live with that.
        What is the greatest difficulty, is the blocking routing between pins 
and there
just has to be compromise.
        In custom made asics I advise strongly that the designer and layouter 
actively
involve in the pin layout of the ASIC. This has been my practice and is very
fruitful.

3.      The HF capacitors (ceramic) should not have series resonance in the 
region of
the clock frequencies and even not in the region of the rise and fall times.
        Fortunately in the last few years there are an abundance of suppliers 
with
small (0402, 0603) 10 - 100nF that are RF performance.
        As was mentioned they should be distributed around the ASIC, preferrably
internally on the opposing side of the board with low inductance vias. One
additional constraint in the positioning of the capacitors is to reduce
length/area of the decoupling loop since this causes radiation and
mutual-inductive crosstalk.

Hope this is of some help.

Georg Ramsch wrote:
> 
> Hello, Martin !
> 
> I am just doing the layout for a FG456 package; it is very time consuming and
> one should not use all pins ( my pcb is 6 layers of copper, 2  are power, 
> rest 4
> layers for signals ).
> 
> Some ideas:
> 
> a) routing the two outer rows / columns on the 1st layer,  reach A3 - A5 / E1 
> -
> E5 etc. with the 2 further signal layers.
>     The NCs  give some advantage.
>     Sometimes it is annoying to to change the schematic every 20 min for 
> better
> routing, but may be worth it.
> 
> b) do not connect every power pin to the power plane, but may be 4 Gnd to 1 
> via
> for example( total 9 Gnd vias at the center );
>     such reducing the swiss cheese effect.
>      If a Gnd planes is just at layer 2, the effect of increased Lvia should 
> not
> be so strong.
>     ==> Comments are welcome!
> 
> c) Having a look at the resonant frequencies of ceramic capacitors shows a 
> range
> of the resonant frequencies
>     between 10 MHz - 50 MHz mostly for 33 - 100nF types.
>     Blocking higher frequencies is possible with embedded capacitance ( 2 - 4
> mil spacing between power planes ).
>     The location of the caps is perhaps not so critical, if such an embedded
> capacitance exists.
> 
>     ==> Can anybody give information about the dependancy of plane impedance 
> and
> the blocking effect of a cap?
> 
> CU
> 
> Georg
> 
> Martin Euredjian wrote:
> 
> > Mark,
> >
> > > What is it about a 1mm pitch device that prevents you from
> > > putting enough capacitors on the board?
> >
> > Where I see a problem is in the inner corner of a package.  I'm not doing
> > the final layout myself, however, I am trying to specify an attainable
> > number of caps in the schematic.  I'm doing a rough layout in order to get
> > at such things as pin assignments (fanout dependant) and the number and type
> > of decoupling caps for some of these large pin count devices.
> >
> > I'm probably missing something very fundamental, so I'd appreciate any and
> > all input on this matter.  I'm looking at the FG456 package.  Each of the
> > inner corners have 4x VCCAUX balls and 4x VCCO balls.  Outside these
> > corners, you can cover most of the VCCO with 0402's between the VCCO via and
> > the corresponding GND via.  However, once you get to the inner corners, you
> > run out of space.  How do you place 8 caps where you can barely fit one.  Of
> > course, I'm going on the assumption (rule?) that you don't want your HF caps
> > centimeters away from these pins, but as close as possible ~ 1-2mm trace
> > max.
> >
> > I've attached a JPEG image depicting the above.  It won't make it onto the
> > list but it should arrive at your off-list email address.
> >
> > Thanks,
> >
> > ===============================
> >  Martin Euredjian
> >   eCinema Systems, Inc.
> >        voice: 661-305-9320
> >        fax:   661-775-4876
> >   martin@xxxxxxxxxxxxxx
> >   www.ecinemasys.com
> > ===============================
> >
> > -- Binary/unsupported file stripped by Ecartis --
> > -- Type: image/jpeg
> > -- File: Decoupling copy.jpg
> >
> > ------------------------------------------------------------------
> > To unsubscribe from si-list:
> > si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
> >
> > or to administer your membership from a web page, go to:
> > http://www.freelists.org/webpage/si-list
> >
> > For help:
> > si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> >
> > List archives are viewable at:
> >                 http://www.freelists.org/archives/si-list
> > or at our remote archives:
> >                 http://groups.yahoo.com/group/si-list/messages
> > Old (prior to June 6, 2001) list archives are viewable at:
> >                 http://www.qsl.net/wb6tpu
> >
> 
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
> 
> or to administer your membership from a web page, go to:
> http://www.freelists.org/webpage/si-list
> 
> For help:
> si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> 
> List archives are viewable at:
>                 http://www.freelists.org/archives/si-list
> or at our remote archives:
>                 http://groups.yahoo.com/group/si-list/messages
> Old (prior to June 6, 2001) list archives are viewable at:
>                 http://www.qsl.net/wb6tpu
>
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages 
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu

Other related posts: