[SI-LIST] Re: Xilinx decoupling

From Mark Alexander:
> I think there's an implicit assumption here that HF
> capacitors must be mounted within the FPGA footprint.
> This is not the case.
...

>> ~ 1-2mm trace max.
> 1-2mm is excessive.  If possible, draw your capacitor lands
> with the via directly against the pad (not trace)
...

From Jeff Seeger:
>> Yes, in many cases the optimal position for these
>> capacitors is within the FPGA footprint,
...

> I should point out that doing this causes pain if you
> are x-ray inspecting your finished boards.  This is not
> to say it can't or shouldn't be done.


There seems to be a disparity between what most SI sources are saying and
what people are doing ("In theory, theory and practice are the same, but in
practice they are not").

Everything I've read and calculated seems to confirm that HF capacitors
placed outside the bounds of a package are mostly useless.  In practical
terms "outside the package" means about 8 to 10 mm away from the power pin
being decoupled.  This means a best-case round trip in the order of 16mm +
vias.  In the FG456 package none of the capacitors servicing the VCCINT pins
would be closer than several mm (maybe one in direct contact with a VCCINT
at each corner).  When I speak of a capacitor servicing a particular pin I
am specifically speaking in terms of HF current.  Yes, at LF and MF there is
no such thing as capacitor->pin assignment, the power planes take care of
supplying current very nicely.

Now, all of this makes me think, and, since I'm not an expert in this field
I have to rely on those who are in order to qualify this thought as having
some merit or not.  A device such as a high density BGA can only receive
operating current from paths entering its footprint from outside it's
periphery.  Power planes are assumed, of course, but local high-frequency
current doesn't come from six inches away.  Has anyone looked at what
happens if all HF capacitance surounds a device on the outside of it's
footprint?  In the case of the device I'm working with, this would mean an
area of about 30x30mm surrounded by about 80 0.01uF chip caps and about
eight low ESR tantalums.  Would this create a sufficiently "stiff" current
availability condition within the encircled area that the device in question
would be able to draw all the current it might require (from HF to LF)?  It
could very well be routing nightmare due to all the vias required, but I
wonder nevertheless.

Thanks,


===============================
 Martin Euredjian
  eCinema Systems, Inc.
       voice: 661-305-9320
       fax:   661-775-4876
  martin@xxxxxxxxxxxxxx
  www.ecinemasys.com
===============================




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