[SI-LIST] Re: Xilinx decoupling

From: Jeff Seeger <jseeger@xxxxxxxxxxxxxx>
To: mark.alexander@xxxxxxxxxx
Date: Mon, 16 Dec 2002 14:25:12 -0500

Mark Alexander wrote:
> 
> snip <
> Yes, in many cases the
> optimal position for these capacitors is within the FPGA footprint,
> snip < 

        I should point out that doing this causes pain if you are
        x-ray inspecting your finished boards.  This is not to say
        it can't or shouldn't be done.

-- 
 
      Jeff Seeger                         Applied CAD Knowledge Inc
      Chief Technical Officer                  Tyngsboro, MA  01879
      jseeger "at" appliedcad "dot" com                978 649 9800
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References:

[SI-LIST] Re: Xilinx decoupling
From: Martin Euredjian

[SI-LIST] Re: Xilinx decoupling
From: Mark Alexander

[SI-LIST] Re: Xilinx decoupling

Other related posts: