[SI-LIST] Re: Xilinx decoupling

Dear Martin,

Did you consider a local power plane covering all the supply pins in layer 
1 with layer 2 as a solid ground plane. If seperate  supplies are required 
you may connect  the most noisy pins or balls to the layer 1 local power 
plane an the other  to such a small local plane in e.g. layer 3. In this 
way only a few decoupling capacitors at the solder side may be required. 
These capacitors should be connected to the local power planes and ground 
plane with vias in such a way that the loop inductance is as low as 
possible.  For instance by a via configuration that forms a coaxial 
connection. I once described a circular mltilayer capacitor with a coaxial 
terminal construction for a very low self-inductance, but it was already 
inventend by Murata. Their special multi layer capacitor is a nice soution 
for BGAs but I do not know whether this type is already available.
 
BTW pins or balls that internally already are connected may be combined to 
the same power plane and as such only will need one capacitor

Kind regards
Boris Traa

System design engineer EMC

Philips Semiconductors BV, dep. SLE
Location A320/301
PObox 80021, 5600JZ
Eindhoven, The Netherlands
Tel: ++ 31 40 27 22249
Fax: ++ 31 40 27 23238
E-mail:  boris.traa@xxxxxxxxxxxx Seri: btraa@nlsce1









"Martin Euredjian" <martin@xxxxxxxxxxxxxx>
Sent by: 
si-list-bounce@xxxxxxxxxxxxx
16-12-2002 18:21
Please respond to martin

 
        To:     "si-list" <si-list@xxxxxxxxxxxxx>
        cc:     (bcc: Boris Traa/EHV/SC/PHILIPS)
        Subject:        [SI-LIST] Xilinx decoupling
        Classification: 




Yet another question on decoupling...

The "capacitor per power pin" recommendation can be found in datasheets
across the globe.  This, coupled to the "number of simultaneous switching
outputs" metric can result in some pretty hilarious BOM's.  The tip of the
iceberg are application notes that are just plain wrong ... I ran across 
one
where you can plug any number into the rise-time portion of the equations
and still get the same number and size of caps as the output.

On the other hand, there's the practicality of placing N number of caps
close enough to the device in question.  Tantalums are not a problem; as
long as they are within a couple of cm from the device everything is fine.
Now, with small-valued chip caps the issue is different.  With 1mm (or 
less)
BGA pitch devices it is physically impossible to reach the "capacitor per
pin" recommendation we were all programmed with in school.  Even if you 
use
tiny 0201 sized devices, it is impossible to cover every power pin unless
you are willing to give-up something. For example, not using some of the 
I/O
pins could eliminate vias --or turn them to GND connections-- which would
open-up room for on the back side.

I've looked at boards that only have but a handful, maybe eight or so, 
caps
under the device and only one tantalum instead of the eight or so you 
might
need if you follow data sheets/app notes.  I haven't seen many with 0201
parts yet, although I'm pretty sure they are out there.

The question, then, is:
What is the practical real-world execution of decoupling such devices?

Thanks,

===============================
 Martin Euredjian
  eCinema Systems, Inc.
       voice: 661-305-9320
       fax:   661-775-4876
  martin@xxxxxxxxxxxxxx
  www.ecinemasys.com
===============================




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