[SI-LIST] Re: Traces don't cause EMI - really?

  • From: Chris Cheng <chris.cheng@xxxxxxxxxxxx>
  • To: "'leeritchey@xxxxxxxxxxxxx'" <leeritchey@xxxxxxxxxxxxx>,bdewitt@xxxxxxxxxxxxx, Charles Grasso <Charles.Grasso@xxxxxxxxxxxx>,si-list@xxxxxxxxxxxxx
  • Date: Tue, 14 Oct 2003 15:16:54 -0700

Ok, I will give an example of both transmission line emitting EMI and why
tight coupling differential pairs solve the problem.

Take your best package with the lowest possible lead inductance. Run your
signal trace on the surface as microstrip. Reference it to a perfect solid
plane as you like to mention. Except the solid plane is tied to a power
plane that has nothing to do with the I/O power or ground. Guess what, you
will see both pwr/gnd bounce and large EMI emission because the image
current flowing on the reference plane does not have a low impedance path to
return to the I/O source. This is a classic example of so many experts in
this message board like to sell you thin dielectric core bypass planes
because it is the best way to provide the low impedance for the image
current to return after you make the mistake of referencing signals to the
wrong plane. You can dig up lots of papers that claim how EMI is changed
with the additional of thin core. What the paper won't tell you is if you
reference the microstrip with the proper I/O power or ground and proper on
die decoupling, the EMI and SSO noise will be even smaller. I have seen this
in real design and fixed the problem with the proper referencing plane.

Now, to further the claim of advantage of coupling differential signals, run
a differential pair on top of the same reference plane that has nothing to
do with the I/O power or ground. The SSO and the EMI will be substantially
decreased. Why ? The image current of the differential signals on the
reference plane cancels each other out due to the tight loop and there is no
large return current other than the common mode which can be decoupled at
the terminator. I am not a brag but in designs where layers count is tight
and I am forced to bump signals up to top layer with core power planes, I
have success in taking all the differential clocks out to that layer while
keeping the single ended highspeed buses as striplines with proper reference
plane inside. The key is tight coupling on the differential clock on the
outer layer.

What do you think ?

-----Original Message-----
From: Lee Ritchey [mailto:leeritchey@xxxxxxxxxxxxx]
Sent: Monday, October 13, 2003 7:07 AM
To: bdewitt@xxxxxxxxxxxxx; Charles Grasso; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Traces don't cause EMI - really?


Brent,

I've tried several times to measure significant emissions from a single
transmission line travelling over a plane at the distances above the plane
one uses to create signal paths for logic circuits, the topic of concern in
this thread, with no luck.

I welcome measurements from others that supports the statement that traces
over planes are significant sources of EMI.  So far, no one has presented
such evidence.  Lacking such evidence, how can anyone make such claims?

True, this thread concerns differential signals, but how are they different
from single ended signals?

True, Doug Brooks' paper didn't set out to measure emissions from traces on
outer layers, but it did state that measured emissions were 30+ db below
what a mono pole would emit.   

In all my measurements, the lead frames of the ICs are the big radiators. 
They make nice antennas.  They stick up above the PCB and they have
significant transient currents flowing through them, especially the power
leads.  Check out a PLCC with a near field probe sometime.

Time for some measurements from those who want this discussion to seriously
come to any conclusion.  Anyone have any?

Lee


> > "Second, traces that run over continuous planes don't cause EMI,
> > differenrtial or otherwise. Again, there are many papers that
demonstrate
> > this as well."
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