Posts for si-list, 10-2003

Browse: Last Month: 09-2003 Main Archive Page Next Month: 11-2003

» [SI-LIST] Re: Repeaters in DSM interconnects -
» [SI-LIST] Re: [IS-LIST] Using Scattering Parameters with PSPICE -
» [SI-LIST] Using Scattering Parameters with PSPICE -
» [SI-LIST] Re: N-port problem in interconnects -
» [SI-LIST] Re: Question on DIMM's -
» [SI-LIST] Re: Question on DIMM's -
» [SI-LIST] Re: N-port problem in interconnects -
» [SI-LIST] Question on DIMM's -
» [SI-LIST] PCI trace impedance -
» [SI-LIST] Repeaters in DSM interconnects -
» [SI-LIST] Re: Full device simulator? -
» [SI-LIST] unsubscribe -
» [SI-LIST] Re: Full device simulator? -
» [SI-LIST] Full device simulator? -
» [SI-LIST] Re: N-port problem in interconnects -
» [SI-LIST] N-port problem in interconnects -
» [SI-LIST] Re: Can you tell me some books or papers about class C amplifier? -
» [SI-LIST] SI opportunity at Dell Austin, along with other engineeringposit ions -
» [SI-LIST] Can you tell me some books or papers about class C amplifier? -
» [SI-LIST] Question about AC analysis for weak inversion MOS using HSPICE -
» [SI-LIST] Re: Books/references on power/ground distribution -
» [SI-LIST] Re: 40 Gb/s serial link driver -
» [SI-LIST] Re: 40 Gb/s serial link driver -
» [SI-LIST] Re: 40 Gb/s serial link driver -
» [SI-LIST] New web site for si-list related papers and documents -
» [SI-LIST] Re: 40 Gb/s serial link driver -
» [SI-LIST] Re: 40 Gb/s serial link driver -
» [SI-LIST] Re: 3.125Gpbs Based backplane solutions -
» [SI-LIST] Re: 40 Gb/s serial link driver -
» [SI-LIST] 40 Gb/s serial link driver -
» [SI-LIST] Re: 3.125Gpbs Based backplane solutions -
» [SI-LIST] SI opportunity -
» [SI-LIST] Signal Integrity Secrets -- Revealed! -
» [SI-LIST] Re: Books/references on power/ground distribution -
» [SI-LIST] Fwd: Re: Digest Number 885 -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Books/references on power/ground distribution -
» [SI-LIST] Re: Digest Number 885 -
» [SI-LIST] Re: What are the differencs between W, T and U-element of a tranmission line model? -
» [SI-LIST] Re: Complex voltage division in Hspice? -
» [SI-LIST] Re: What are the differences between W, T and U-element of a transmission line model? -
» [SI-LIST] Re: How to build a variable resistor in HSPICE -
» [SI-LIST] Re: Sacrificial ground: Is it useful? -
» [SI-LIST] Re: What are the differencs between W, T and U-element of a tranmission line model? -
» [SI-LIST] Re: What are the differencs between W, T and U-elementof a tranmission line model? -
» [SI-LIST] About the limit of minimum length -
» [SI-LIST] Re: Sacrificial ground: Is it useful? -
» [SI-LIST] Field-solver -
» [SI-LIST] testing -
» [SI-LIST] Re: Sacrificial ground: Is it useful? -
» [SI-LIST] Re: Complex voltage division in Hspice? -
» [SI-LIST] Re: Complex voltage division in Hspice? -
» [SI-LIST] Re: Complex voltage division in Hspice? -
» [SI-LIST] Re: Complex voltage division in Hspice? -
» [SI-LIST] Complex voltage division in Hspice? -
» [SI-LIST] Components Assembly Cost -
» [SI-LIST] Re: Sacrificial ground: Is it useful? -
» [SI-LIST] Re: SI contract opportunity in California -
» [SI-LIST] Re: SI contract opportunity in California -
» [SI-LIST] Re: SI contract opportunity in California -
» [SI-LIST] Re: SI contract opportunity in California -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] BiTS Burn-in & Test Socket Workshop - Call For Presentations abstract submission deadline extension -
» [SI-LIST] SI contract opportunity in California -
» [SI-LIST] Sacrificial ground: Is it useful? -
» [SI-LIST] -
» [SI-LIST] Re: TDR VTT Question -
» [SI-LIST] Re: TDR VTT Question -
» [SI-LIST] Re: What are the differencs between W, T and U-element of atranmission line model? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] TDR VTT Question -
» [SI-LIST] Re: Why crosstalk calculation does not count into trace width? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] SSTL2 class-II twice or thrice of Class-I -
» [SI-LIST] SPI -4 interface -
» [SI-LIST] Re: Why crosstalk calculation does not count into trace width? -
» [SI-LIST] Re: Why crosstalk calculation does not count into trace width? -
» [SI-LIST] Re: Why crosstalk calculation does not count into trace width? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: KPn and KPp in Level 49 spice transistor model -
» [SI-LIST] Re: SI impact on BGA Ball placement and pwr/gnd ratios -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Lee - Paper avaiable on RMCEMC website. -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: SI impact on BGA Ball placement and pwr/gnd ratios -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Differential Signalling through Tri-axial Cable ?.... -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] 3.125Gpbs Based backplane solutions -
» [SI-LIST] Re: Power plane frequency range and noise level -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] SI impact on BGA Ball placement and pwr/gnd ratios -
» [SI-LIST] Re: Power plane frequency range and noise level -
» [SI-LIST] Why crosstalk calculation does not count into trace width? -
» [SI-LIST] Re: Power plane frequency range and noise level -
» [SI-LIST] Power plane frequency range and noise level -
» [SI-LIST] Re: PCB Radiated Emissions paper available for download -
» [SI-LIST] Re: Rigid-Flex Testing -
» [SI-LIST] Re: Ethernet simulations -
» [SI-LIST] Ethernet simulations -
» [SI-LIST] Re: Rigid-Flex Testing -
» [SI-LIST] Re: Rigid-Flex Testing -
» [SI-LIST] Re: Rigid-Flex Testing -
» [SI-LIST] Re: ERROR CALCULATIONS -
» [SI-LIST] REMINDER Oct 27 & 28 - NESA Seminar: "Signal Integrity Principles for Gigabit Connector, Cable and Semiconductor Package Designs" -
» [SI-LIST] Re: ERROR CALCULATIONS -
» [SI-LIST] Differential Signalling through Tri-axial Cable ?.... -
» [SI-LIST] Re: Rigid-Flex Testing -
» [SI-LIST] ERROR CALCULATIONS -
» [SI-LIST] Re: Rigid-Flex Testing -
» [SI-LIST] Rigid-Flex Testing -
» [SI-LIST] A couple comments on list etiquette and respect for others opinions -
» [SI-LIST] How to compile netlist in DRACUlA -
» [SI-LIST] Re: A question -
» [SI-LIST] Please unsubscribe -
» [SI-LIST] Re: A question -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] What's the reason for the following layout rule? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] What are the differencs between W, T and U-element of a tranmission line model? -
» [SI-LIST] Re: test point position -
» [SI-LIST] test point position -
» [SI-LIST] Unsubscribe -
» [SI-LIST] PCB Radiated Emissions paper available for download -
» [SI-LIST] Re: KPn and KPp in Level 49 spice transistor model -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] LINPAR dos user-defined structure -
» [SI-LIST] Re: Paper reference to download -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] how to use star_rcxt to extract spf ? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] ebd file simulation -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Help to see the DDR differential clock waveform in PCB -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] KPn and KPp in Level 49 spice transistor model -
» [SI-LIST] Re: Timing analaysis for Interfaces -
» [SI-LIST] EMC Society papers available on CD-ROM -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: LNAs -
» [SI-LIST] Signal Integrity Seminar October 24, San Jose -
» [SI-LIST] Re: LNAs -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Modelling semiconductors in 2D field solvers -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: RLGC Parameters -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: A question -
» [SI-LIST] Re: si-list Digest V3 #305 -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: How to import hspice into ADS -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: si-list Digest V3 #305 -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: s-parameter citi file format -
» [SI-LIST] Crystal Oscillator design -
» [SI-LIST] Re: SerDes vs. PHY for Gigabit Ethernet -
» [SI-LIST] Re: s-parameter citi file format -
» [SI-LIST] SerDes vs. PHY for Gigabit Ethernet -
» [SI-LIST] Re: RLGC Parameters -
» [SI-LIST] Re: s-parameter citi file format -
» [SI-LIST] PCI-X/PCI Ground/Power Voltage Drop -
» [SI-LIST] Re: Diff Impedance and its noise immunity. -
» [SI-LIST] Re: s-parameter citi file format -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: A question -
» [SI-LIST] A question -
» [SI-LIST] s-parameter citi file format -
» [SI-LIST] Re: Active components on a highspeed backplane -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] How to import hspice into ADS -
» [SI-LIST] Re: 50ohm SSTL2 Tx -
» [SI-LIST] Re: PCI and PCI-X bus noise -
» [SI-LIST] Re: si-list: winbery@comcast.net post needs approval -
» [SI-LIST] Re: Active components on a highspeed backplane -
» [SI-LIST] RLGC Parameters -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Active components on a highspeed backplane -
» [SI-LIST] Re: Active components on a highspeed backplane -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Active components on a highspeed backplane -
» [SI-LIST] Re: Traces don't cause EMI - really?--oops -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: PCI and PCI-X bus noise -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: 50ohm SSTL2 Tx -
» [SI-LIST] Re: How to use common mode chock to elimate Common-mode noise ? -
» [SI-LIST] Diff Impedance and its noise immunity. -
» [SI-LIST] Re: PCI and PCI-X bus noise -
» [SI-LIST] ESD wire -
» [SI-LIST] about ethernet phy interface question -
» [SI-LIST] How to set I/O pins to high-Z state -
» [SI-LIST] Need Information On Limiting Amplifier Design -
» [SI-LIST] Re: circuit simulations -
» [SI-LIST] 50ohm SSTL2 Tx -
» [SI-LIST] Re: ESD through Ferrite core -
» [SI-LIST] circuit simulations -
» [SI-LIST] where can I get a free eval HSPICE or portion of it? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: TIME TO VM question! -
» [SI-LIST] PCI and PCI-X Bus Noise Followup -
» [SI-LIST] Re: Diff.Pairs - Return current distribution -
» [SI-LIST] Re: need of voltage regulator for SPARTAN-III VCCINT supply -
» [SI-LIST] permeabilty -
» [SI-LIST] Re: PCI and PCI-X bus noise -
» [SI-LIST] Re: Hspice differential Tline -
» [SI-LIST] Re: Hspice differential Tline -
» [SI-LIST] Re: Diff.Pairs - Return current distribution -
» [SI-LIST] FYI: "Right By Design" Seminar -
» [SI-LIST] Diff.Pairs - Return current distribution -
» [SI-LIST] Re: PCI and PCI-X bus noise -
» [SI-LIST] Terrmination techniques in SoCs ??? -
» [SI-LIST] Re: PCI and PCI-X bus noise -
» [SI-LIST] LNAs -
» [SI-LIST] TIME TO VM question! -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] need of voltage regulator for SPARTAN-III VCCINT supply -
» [SI-LIST] ESD through Ferrite core -
» [SI-LIST] Re: Diff.Pairs - Return current distribution -
» [SI-LIST] Re: Hspice differential Tline -
» [SI-LIST] Re: Hspice differential Tline -
» [SI-LIST] Re: How to build a variable resistor in HSPICE -
» [SI-LIST] Re: DDR-2 DQS -
» [SI-LIST] Hspice differential Tline -
» [SI-LIST] Re: How to build a variable resistor in HSPICE -
» [SI-LIST] Re: How to build a variable resistor in HSPICE -
» [SI-LIST] How to build a variable resistor in HSPICE -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: DDR-2 DQS -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] modeling and simulating transmission line -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: ESD protection devices -
» [SI-LIST] PCI and PCI-X bus noise -
» [SI-LIST] Re: ESD protection devices -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] VCCINT 1.2 Vlot For Spartan3 Device -
» [SI-LIST] Re: ESD protection devices -
» [SI-LIST] Re: ESD protection devices -
» [SI-LIST] Re: ESD protection devices -
» [SI-LIST] Re: ESD protection devices -
» [SI-LIST] Re: ESD protection devices -
» [SI-LIST] ESD protection devices -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] DDR-2 DQS -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Emi from traces - paper eference -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] SI Job Opportunity at Extreme Networks - Req # 751 -
» [SI-LIST] Re: Attenuation in Lumped and Disstributed model -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Traces don't cause EMI - really?...and Diff. pairs -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Attenuation in Lumped and Disstributed model -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: PS decoupling for QFP and similars -
» [SI-LIST] Specs. of a double-sided PCI board -
» [SI-LIST] Re: XTK issue -
» [SI-LIST] XTK issue -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] Re: Traces don't cause EMI - really? -
» [SI-LIST] RMCEMC September Meeting slides available for download -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Single ended via analysis -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: PS decoupling for QFP and similars -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Papers - a little help, please -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Papers - a little help, please -
» [SI-LIST] Re: PS decoupling for QFP and similars -
» [SI-LIST] Traces don't cause EMI - really? -
» [SI-LIST] PS decoupling for QFP and similars -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] DDR2- 800MBPS timing requirements -
» [SI-LIST] Re: Heisenberg and signal measurements -
» [SI-LIST] unsubscribe -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs (clarification) -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Heisenberg and signal measurements -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: How to use common mode chock to elimate Common-mode noise ? -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Couple of Questions for a starter -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: How to use common mode chock to elimate Common-mode noise ? -
» [SI-LIST] OrCAD to Concept HDL Schematics conversions -
» [SI-LIST] Re: Capacitors and Anti-resonance -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] How to use common mode chock to elimate Common-mode noise ? -
» [SI-LIST] Re: Hardware Design guru - FYI -
» [SI-LIST] TRANSISTORS ? -
» [SI-LIST] Re: operational amplifiers -
» [SI-LIST] Re: operational amplifiers -
» [SI-LIST] Re: rf boards -
» [SI-LIST] magnetic permeability -
» [SI-LIST] call for papers -
» [SI-LIST] magnetic permeability in dielectric loss -
» [SI-LIST] Re: Antenna currents and digital Ground -
» [SI-LIST] AD9901 -
» [SI-LIST] Re: operational amplifiers -
» [SI-LIST] rf boards -
» [SI-LIST] operational amplifiers -
» [SI-LIST] FW: Diff. Pairs -
» [SI-LIST] Re: Very Basic question -
» [SI-LIST] Re: Diff. Pairs -
» [SI-LIST] Re: Antenna currents and digital Ground -
» [SI-LIST] Very Basic question -
» [SI-LIST] Antenna currents and digital Ground -
» [SI-LIST] implemented peeling algorithm for TDR -
» [SI-LIST] Diff. Pairs -
» [SI-LIST] Re: Diff. Pairs -
» [SI-LIST] Re: Diff. Pairs -
» [SI-LIST] Re: Diff. Pairs -
» [SI-LIST] Re: Diff. Pairs -
» [SI-LIST] Re: Diff. Pairs -
» [SI-LIST] Re: Diff. Pairs -
» [SI-LIST] Re: Diff. Pairs -
» [SI-LIST] Heisenberg and signal measurements -
» [SI-LIST] Re: Impedance Uniformity -
» [SI-LIST] Impedance Uniformity -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Looking for Job -
» [SI-LIST] Re: A question about reference plane in gigabit ethernet design! -
» [SI-LIST] Re: Diff Pairs -
» [SI-LIST] Re: BBC Presentation--James Clark Maxwell -
» [SI-LIST] Re: Diff Pairs -
» [SI-LIST] Re: HSPICE - Deciding Max. route length -
» [SI-LIST] Re: BBC Presentation--James Clark Maxwell -
» [SI-LIST] Re: BBC Presentation--James Clark Maxwell -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff. Pairs -
» [SI-LIST] Re: Diff Pairs -
» [SI-LIST] Re: [Fwd: [IBIS-Users] static/dynamic overshoot/undershoot definition] -
» [SI-LIST] Re: Diff. Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff. Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] IBIS Interconnect Modeling (ICM) Specification 1.0 now available -
» [SI-LIST] Re: ESD Issues -
» [SI-LIST] ESD Issues -
» [SI-LIST] Re: negative propagation delay -
» [SI-LIST] Re: negative propagation delay -
» [SI-LIST] Re: A question about reference plane in gigabit ethernet design! -
» [SI-LIST] Re: negative propagation delay -
» [SI-LIST] Re: A question about reference plane in gigabit ethernet design! -
» [SI-LIST] Fwd: Re: High Impedance Traces are prone to Radio Frequency Interference -
» [SI-LIST] Re: power consuming of OSC -
» [SI-LIST] A question about reference plane in gigabit ethernet design! -
» [SI-LIST] Re: On choosing center tap capacitor value for differential termination -
» [SI-LIST] Re: Guard traces for differential pairs -
» [SI-LIST] Congratulations on a needed book -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: Guard traces for differential pairs -
» [SI-LIST] Re: On choosing center tap capacitor value for differential termination -
» [SI-LIST] Re: negative propagation delay -
» [SI-LIST] Re: HyperLynx vs Hspice -
» [SI-LIST] Re: negative propagation delay -
» [SI-LIST] Re: Diff.Pairs -
» [SI-LIST] Re: negative propagation delay -
» [SI-LIST] Re: negative propagation delay -
» [SI-LIST] negative propagation delay -
» [SI-LIST] Diff.Pairs -
» [SI-LIST] Re: HyperLynx vs Hspice -
» [SI-LIST] Re: Off topic -- Electrical Component Abbreviations -
» [SI-LIST] Re: USB 2.0 testing -
» [SI-LIST] UltraCAD's calculator bug update -
» [SI-LIST] Re: On choosing center tap capacitor value for differential termination -
» [SI-LIST] Re: On choosing center tap capacitor value for differentialtermination -
» [SI-LIST] Re: On choosing center tap capacitor value for differential termination -
» [SI-LIST] Re: Off topic -- Electrical Component Abbreviations -
» [SI-LIST] Re: Off topic -- Electrical Component Abbreviations -
» [SI-LIST] Off topic -- Electrical Component Abbreviations -
» [SI-LIST] Re: On choosing center tap capacitor value for differential termination -
» [SI-LIST] Re: SREC utility -
» [SI-LIST] Re: Hardware Design guru - FYI -
» [SI-LIST] On choosing center tap capacitor value for differential termination -
» [SI-LIST] Re: SREC utility -
» [SI-LIST] SREC utility -
» [SI-LIST] Re: Hardware Design guru - FYI -
» [SI-LIST] Ansoft Global Seminars -
» [SI-LIST] Antwort: Simulating Wiring Harnesses and Cables. -
» [SI-LIST] Compact PCI backplane overshoot/undershoot diode array -