[SI-LIST] Re: TCOmin < external buffer delay
- From: "Peterson, James F (FL51)" <james.f.peterson@xxxxxxxxxxxxx>
- To: SI freelist <si-list@xxxxxxxxxxxxx>
- Date: Thu, 20 Oct 2005 04:40:55 -0700
B.R.,
When you say "common clock signal", I assume you mean a data signal that
leaves one flop and goes to another flop, and that both of these flops use a
common clock but are separated by a routed trace on a pcb.
If your ibis model has the same load as the datasheet, and you have a SI
simulator that corrects for this, then the negative delay is correct. What
to do with it? It goes into your overall hold time equation :
Th(margin)=Tco(min) + PCBdelay - CLKskew - Rcvr(hold)
In the above equation, your "PCBdelay" is negative - usually its a positive
number, but yours has been "load adjusted" (the key to understanding this is
to understand what "load adjusted" means, and it is out of the scope of an
email). if your answer is negative, then you have a hold time problem and
slowing down a clock can not cure it. The way to solve this problem is to
add copper to the PCB route, so that the answer is no longer negative.
(we've talked about this before on the SI-List, check the archives using a
words like "negative delay".)
regards,
Jim Peterson
Honeywell
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx
<mailto:si-list-bounce@xxxxxxxxxxxxx> ] On Behalf Of Yuming Cheng
Sent: Wednesday, October 19, 2005 9:56 PM
To: SI freelist
Subject: [SI-LIST] TCOmin < external buffer delay
Hello all,
When I analyze a common clok signal. The datasheet gives Max TCO and Min
TCO.
According to the TCO measurement, TCO include Internal Logic delay and
external buffer delay. In order to not double count the external buffer
delay portion of Tco.
I subtract it from TCO to get the internal logic delay.
I use the IBIS model and the measurement circuit to measure the external
buffer delay.
When calculate the setup margin, I use Max Tco. The internal logic delay is
positive.
When calculate the hold margin, I use Min TCO.
Because the external buffer delay is large than Min TCO. Then the internal
Logic delay is negative.
Do I use the negavtive Internal Logic Delay or round up it to zero to
calculate the hold margin?
B.R.
Astrom
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