Posts for si-list, 10-2005

Browse: Last Month: 09-2005 Main Archive Page Next Month: 11-2005

» [SI-LIST] Re: Can L12 ever exceed L1 or L2 ?? -
» [SI-LIST] High-speed serial data transfer -
» [SI-LIST] Openning in Marvell Storage Networking Group -
» [SI-LIST] Re: Can L12 ever exceed L1 or L2 ?? -
» [SI-LIST] Re: REPOST: SI Question 3 of 3: Power plane fingers over split in ground plane -
» [SI-LIST] Re: REPOST: SI Question 2 of 3: Differential clock lines over split in ground plane -
» [SI-LIST] Re: REPOST: SI Question 1 of 3: "Quiet" lines over split in ground plane -
» [SI-LIST] Signal Integrity Intern at Cisco's RTP, NC facility: -
» [SI-LIST] REPOST: SI Question 3 of 3: Power plane fingers over split in ground plane -
» [SI-LIST] REPOST: SI Question 2 of 3: Differential clock lines over split in ground plane -
» [SI-LIST] REPOST: SI Question 1 of 3: "Quiet" lines over split in ground plane -
» [SI-LIST] Re: Can L12 ever exceed L1 or L2 ?? -
» [SI-LIST] Re: Can L12 ever exceed L1 or L2 ?? -
» [SI-LIST] Re: Can L12 ever exceed L1 or L2 ?? -
» [SI-LIST] Re: Can L12 ever exceed L1 or L2 ?? -
» [SI-LIST] I'm Back -
» [SI-LIST] Re: Can L12 ever exceed L1 or L2 ?? -
» [SI-LIST] Re: Can L12 ever exceed L1 or L2 ?? -
» [SI-LIST] Re: Can L12 ever exceed L1 or L2 ?? -
» [SI-LIST] Can L12 ever exceed L1 or L2 ?? -
» [SI-LIST] Re: Can L12 ever exceed L1 or L2 ?? -
» [SI-LIST] Re: Can L12 ever exceed L1 or L2 ?? -
» [SI-LIST] Re: Can L12 ever exceed L1 or L2 ?? -
» [SI-LIST] Re: Can L12 ever exceed L1 or L2 ?? -
» [SI-LIST] Can L12 ever exceed L1 or L2 ?? -
» [SI-LIST] SI Question 1 of 3: "Quiet" lines over split in ground plane -
» [SI-LIST] SI Question 2 of 3: Differential clock lines over split in ground plane -
» [SI-LIST] SI Question 3 of 3: Power plane fingers over split in ground plane -
» [SI-LIST] Re: Common-mode return path for differential signals. -
» [SI-LIST] Re: quenching ugly spikes? -
» [SI-LIST] Re: clc001 and lvds -
» [SI-LIST] Re: quenching ugly spikes? -
» [SI-LIST] Re: quenching ugly spikes? -
» [SI-LIST] quenching ugly spikes? -
» [SI-LIST] Signal Integrity workshop at CST -
» [SI-LIST] Re: clc001 and lvds -
» [SI-LIST] clc001 and lvds -
» [SI-LIST] new number -
» [SI-LIST] Re: Common-mode return path for differential signals. -
» [SI-LIST] Re: Common-mode return path for differential signals. -
» [SI-LIST] Re: Common-mode return path for differential signals. -
» [SI-LIST] Re: Power plane coupling -
» [SI-LIST] Re: Power plane coupling -
» [SI-LIST] Re: Power plane coupling -
» [SI-LIST] Re: Power plane coupling -
» [SI-LIST] Re: which test i have to do? -
» [SI-LIST] Re: About EMI/EMC book -
» [SI-LIST] Re: About EMI/EMC book -
» [SI-LIST] Re: Power plane coupling -
» [SI-LIST] Re: About EMI/EMC book -
» [SI-LIST] Re: About EMI/EMC book -
» [SI-LIST] High Speed connector -
» [SI-LIST] which test i have to do? -
» [SI-LIST] Asian IBIS Summit Fourth Announcement -
» [SI-LIST] About EMI/EMC book -
» [SI-LIST] Re: SSTL/DDR series termination -
» [SI-LIST] Re: SSTL/DDR series termination -
» [SI-LIST] Re: [SI-LIST Microstrip Loss Correlation: Need to look at TDR -
» [SI-LIST] Re: Power plane coupling -
» [SI-LIST] Re: Displaying eye pattern in an oscilloscope? -
» [SI-LIST] Re: Displaying eye pattern in an oscilloscope? -
» [SI-LIST] Re: Displaying eye pattern in an oscilloscope? -
» [SI-LIST] Re: SSTL/DDR series termination -
» [SI-LIST] Re: Displaying eye pattern in an oscilloscope? -
» [SI-LIST] Re: Displaying eye pattern in an oscilloscope? -
» [SI-LIST] Re: Displaying eye pattern in an oscilloscope? -
» [SI-LIST] Re: Displaying eye pattern in an oscilloscope? -
» [SI-LIST] Re: SSTL/DDR series termination -
» [SI-LIST] Displaying eye pattern in an oscilloscope? -
» [SI-LIST] Re: Power plane coupling -
» [SI-LIST] Re: Power plane coupling -
» [SI-LIST] Re: Microstrip Loss Correlation -
» [SI-LIST] Re: Power plane coupling -
» [SI-LIST] Re: SSTL/DDR series termination -
» [SI-LIST] Re: IBIS for DDR2 DIMM -
» [SI-LIST] Re: Microstrip Loss Correlation -
» [SI-LIST] Re: Power plane coupling -
» [SI-LIST] Re: SSTL/DDR series termination -
» [SI-LIST] Re: Microstrip Loss Correlation -
» [SI-LIST] Re: Microstrip Loss Correlation -
» [SI-LIST] Re: TCOmin < external buffer delay -
» [SI-LIST] Re: SSTL/DDR series termination -
» [SI-LIST] Microstrip Loss Correlation -
» [SI-LIST] SSTL/DDR series termination -
» [SI-LIST] Re: TCOmin < external buffer delay -
» [SI-LIST] Re: IBIS for DDR2 DIMM -
» [SI-LIST] Re: TCOmin < external buffer delay -
» [SI-LIST] Re: TCOmin < external buffer delay -
» [SI-LIST] IBIS for DDR2 DIMM -
» [SI-LIST] Re: TCOmin < external buffer delay -
» [SI-LIST] Re: TCOmin < external buffer delay -
» [SI-LIST] Re: Power plane coupling -
» [SI-LIST] Re: TCOmin < external buffer delay -
» [SI-LIST] Re: TEK or ex-HP, that is the question -
» [SI-LIST] Re: Transmission lines reflections again -
» [SI-LIST] Re: Transmission lines reflections again -
» [SI-LIST] Re: Transmission lines reflections again -
» [SI-LIST] Job Opening - SI Contractor Position -
» [SI-LIST] Re: Multimedia Topics -
» [SI-LIST] Re: Multimedia Topics -
» [SI-LIST] Re: TCOmin < external buffer delay -
» [SI-LIST] Re: Transmission lines reflections again -
» [SI-LIST] Re: TCOmin < external buffer delay -
» [SI-LIST] Power plane coupling -
» [SI-LIST] Multimedia Topics -
» [SI-LIST] Re: TCOmin < external buffer delay -
» [SI-LIST] TEK or ex-HP, that is the question -
» [SI-LIST] TCOmin < external buffer delay -
» [SI-LIST] System-Level Power Integrity - Free Online Seminar hosted by Sigrity, Inc. with Dr. Howard Johnson (Nov 9, 2005) -
» [SI-LIST] System-Level Power Integrity - Free Online Seminar hosted by Sigrity, Inc. with Dr. Howard Johnson (Nov 9, 2005) -
» [SI-LIST] Re: Transmission lines reflections again -
» [SI-LIST] Re: Transmission lines reflections again -
» [SI-LIST] Re: Transmission lines reflections again -
» [SI-LIST] Re: Transmission lines reflections again -
» [SI-LIST] Re: Transmission lines reflections again -
» [SI-LIST] Transmission lines reflections again -
» [SI-LIST] Oscilloscopes Question -
» [SI-LIST] Re: IBIS model Tr accuracy -
» [SI-LIST] Re: IBIS model Tr accuracy -
» [SI-LIST] Re: IBIS model Tr accuracy -
» [SI-LIST] Re: IBIS model Tr accuracy -
» [SI-LIST] Re: IBIS model Tr accuracy -
» [SI-LIST] Re: IBIS model Tr accuracy -
» [SI-LIST] Signal Integrity Opportunities in Cisco India -
» [SI-LIST] Re: IBIS model Tr accuracy -
» [SI-LIST] IBIS model Tr accuracy -
» [SI-LIST] Re: IBIS question: Test Load for Differential Clock -
» [SI-LIST] Re: IBIS question: Test Load for Differential Clock -
» [SI-LIST] Re: IBIS question: Test Load for Differential Clock -
» [SI-LIST] IBIS question: Test Load for Differential Clock -
» [SI-LIST] Bathtub curve tool or script -
» [SI-LIST] Re: spice2IBIS -
» [SI-LIST] Re: Problem with HFSS 9 -
» [SI-LIST] Re: Transmission lines and why there are reflections -
» [SI-LIST] Re: Transmsision lines -
» [SI-LIST] Re: Transmission lines and why there are reflections -
» [SI-LIST] Transmission lines and why there are reflections -
» [SI-LIST] Re: Problem with HFSS 9 -
» [SI-LIST] Re: Transmsision lines -
» [SI-LIST] Re: Transmsision lines -
» [SI-LIST] Re: Problem with HFSS 9 -
» [SI-LIST] Re: Problem with HFSS 9 -
» [SI-LIST] Re: Transmsision lines -
» [SI-LIST] Re: Transmsision lines -
» [SI-LIST] Re: Problem with HFSS 9 -
» [SI-LIST] Transmsision lines -
» [SI-LIST] Problem with HFSS 9 -
» [SI-LIST] Re: pcb stray capacitance -
» [SI-LIST] In HFSS V9.2 -
» [SI-LIST] pcb stray capacitance -
» [SI-LIST] Need help with ibis model for Spansion - AM29DL800B -
» [SI-LIST] Re: s-parameter in cadence -
» [SI-LIST] Re: spice2IBIS -
» [SI-LIST] Re: spice2IBIS -
» [SI-LIST] spice2IBIS -
» [SI-LIST] IV and VT data mismatch -
» [SI-LIST] Asian IBIS Summit Third Announcement -
» [SI-LIST] Re: package S-parameters in IBIS -
» [SI-LIST] Re: package S-parameters in IBIS -
» [SI-LIST] package S-parameters in IBIS -
» [SI-LIST] Re: Undershoot on a cPCI Bus -
» [SI-LIST] Re: s-parameter in cadence -
» [SI-LIST] Re: FYI: posted Excel illustration file for DesignCon East 2005 presentation -
» [SI-LIST] Re: Undershoot on a cPCI Bus -
» [SI-LIST] Undershoot on a cPCI Bus -
» [SI-LIST] Re: Differential Pair Characteristic Impedance Tradeoffs -
» [SI-LIST] Re: s-parameter in cadence -
» [SI-LIST] Recall: s-parameter in cadence -
» [SI-LIST] Re: s-parameter in cadence -
» [SI-LIST] Re: Differential Pair Characteristic Impedance Tradeoffs -
» [SI-LIST] Re: Open traces: how to analyze -
» [SI-LIST] Open traces: how to analyze -
» [SI-LIST] High Speed IO Group Job Openings at Altera. -
» [SI-LIST] Re: Differential Pair Characteristic Impedance Tradeoffs -
» [SI-LIST] Re: FPGA output resistance question -
» [SI-LIST] FPGA output resistance question -
» [SI-LIST] Re: Differential Pair Characteristic Impedance Tradeoffs -
» [SI-LIST] Differential Pair Characteristic Impedance Tradeoffs -
» [SI-LIST] Re: s-parameter in cadence -
» [SI-LIST] Re: s-parameter in cadence -
» [SI-LIST] Re: s-parameter in cadence -
» [SI-LIST] Re: s-parameter in cadence -
» [SI-LIST] Re: s-parameter in cadence -
» [SI-LIST] s-parameter in cadence -
» [SI-LIST] Problems with IBIS2SPICE -
» [SI-LIST] controlling varialbles in test setups -
» [SI-LIST] Santa Clara Valley (SCV) EMC Chapter Meeting--11 October, 2005 -
» [SI-LIST] Re: Jitter Webcast -- Presented jointly by Xilinx and Signal Consulting -
» [SI-LIST] Re: Jitter Webcast -- Presented jointly by Xilinx and Signal Consulting -
» [SI-LIST] Jitter Webcast -- Presented jointly by Xilinx and Signal Consulting -
» [SI-LIST] Re: ROHS Compliance -
» [SI-LIST] ROHS Compliance -