[SI-LIST] Re: TCOmin < external buffer delay

Hi Kai,

If you have different min/typ/max Vdd reference voltages in your IO
model,
these will be used when Allegro PCB SI simulates and stores those buffer
delays. If you have issues with this, please contact me off-line and I
can
show you.

thanks,

Ken




-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Kai Keskinen
Sent: Thursday, October 20, 2005 7:03 PM
To: a.ingraham@xxxxxxxx; SI freelist
Subject: [SI-LIST] Re: TCOmin < external buffer delay

Andy:

Some SI tools, like Cadence Allegro PCB SI, subtract buffer delay from
switching and settling times if you decide you want it to. The buffer
delay is the time when the buffer starts to rise (or fall) at the output
to Vmeasure into the standard load defined in the IBIS file with Vref,
Rref, and Cref. Since the Tco number is defined into the same standard
load, this allows you to avoid double counting the standard load delay
in your timing equations. This is a fairly subtle concept that has to be
learned to get accurate timing numbers from IBIS simulators. The trouble
is that when Vdd changes with slow and fast cases, the tool doesn't take
that into account in calculating buffer delay. For most slower logic,
this is not an issue. When looking at near GHz GDDR interfaces, you need
to run 3 different batch jobs to get the three corner cases properly.

Cheers,

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On
Behalf Of Andrew Ingraham
Sent: Thursday, October 20, 2005 11:56 AM
To: SI freelist
Subject: [SI-LIST] Re: TCOmin < external buffer delay


> According to the TCO measurement, TCO include Internal Logic delay and

> external buffer delay.

I am assuming by "external buffer" you mean the buffer, internal to your
device, that drives the output (external) signal.  Is that what you
meant?

> I use the IBIS model and the measurement circuit to measure the=20
> external buffer delay.

Be careful about this.  IBIS does not necessarily model the external
buffer delay.  The IBIS model may represent just a portion of the
buffer, or it may include more than the buffer.  All you know is that
IBIS describes how the buffer drives the output node.  If you set up a
simulation and measured the delay from the "input" of the IBIS model to
its output, it is a relatively meaningless measurement.

Aside from that, there are many reasons why the internal logic would
appear to have a negative delay.  One is if the device incorporates a
PLL for the clocks.  Another happens because of different loading
conditions.  If your calculation results in a negative number and you
know you are doing the right calculations and using the right methods,
then use the negative number, not zero.

Why do you need to separate the internal logic delay from the output
buffer, anyway?  Why not just treat your device as one block that has no
such boundary?  (Perhaps my assumption above was incorrect?)

Regards,
Andy

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